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Import misc remaining header files from 2013 U-Boot. These will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
109 lines
3.8 KiB
C
109 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __OCTEON_QLM_H__
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#define __OCTEON_QLM_H__
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/* Reference clock selector values for ref_clk_sel */
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#define OCTEON_QLM_REF_CLK_100MHZ 0 /** 100 MHz */
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#define OCTEON_QLM_REF_CLK_125MHZ 1 /** 125 MHz */
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#define OCTEON_QLM_REF_CLK_156MHZ 2 /** 156.25 MHz */
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#define OCTEON_QLM_REF_CLK_161MHZ 3 /** 161.1328125 MHz */
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/**
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* Configure qlm/dlm speed and mode.
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* @param qlm The QLM or DLM to configure
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* @param speed The speed the QLM needs to be configured in Mhz.
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* @param mode The QLM to be configured as SGMII/XAUI/PCIe.
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* @param rc Only used for PCIe, rc = 1 for root complex mode, 0 for EP
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* mode.
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* @param pcie_mode Only used when qlm/dlm are in pcie mode.
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* @param ref_clk_sel Reference clock to use for 70XX where:
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* 0: 100MHz
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* 1: 125MHz
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* 2: 156.25MHz
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* 3: 161.1328125MHz (CN73XX and CN78XX only)
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* @param ref_clk_input This selects which reference clock input to use. For
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* cn70xx:
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* 0: DLMC_REF_CLK0
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* 1: DLMC_REF_CLK1
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* 2: DLM0_REF_CLK
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* cn61xx: (not used)
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* cn78xx/cn76xx/cn73xx:
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* 0: Internal clock (QLM[0-7]_REF_CLK)
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* 1: QLMC_REF_CLK0
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* 2: QLMC_REF_CLK1
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*
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* @return Return 0 on success or -1.
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*
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* @note When the 161MHz clock is used it can only be used for
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* XLAUI mode with a 6316 speed or XFI mode with a 103125 speed.
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* This rate is also only supported for CN73XX and CN78XX.
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*/
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int octeon_configure_qlm(int qlm, int speed, int mode, int rc, int pcie_mode, int ref_clk_sel,
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int ref_clk_input);
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int octeon_configure_qlm_cn78xx(int node, int qlm, int speed, int mode, int rc, int pcie_mode,
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int ref_clk_sel, int ref_clk_input);
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/**
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* Some QLM speeds need to override the default tuning parameters
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*
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* @param node Node to configure
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* @param qlm QLM to configure
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* @param baud_mhz Desired speed in MHz
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* @param lane Lane the apply the tuning parameters
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* @param tx_swing Voltage swing. The higher the value the lower the voltage,
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* the default value is 7.
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* @param tx_pre pre-cursor pre-emphasis
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* @param tx_post post-cursor pre-emphasis.
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* @param tx_gain Transmit gain. Range 0-7
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* @param tx_vboost Transmit voltage boost. Range 0-1
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*/
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void octeon_qlm_tune_per_lane_v3(int node, int qlm, int baud_mhz, int lane, int tx_swing,
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int tx_pre, int tx_post, int tx_gain, int tx_vboost);
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/**
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* Some QLM speeds need to override the default tuning parameters
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*
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* @param node Node to configure
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* @param qlm QLM to configure
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* @param baud_mhz Desired speed in MHz
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* @param tx_swing Voltage swing. The higher the value the lower the voltage,
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* the default value is 7.
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* @param tx_premptap bits [0:3] pre-cursor pre-emphasis, bits[4:8] post-cursor
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* pre-emphasis.
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* @param tx_gain Transmit gain. Range 0-7
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* @param tx_vboost Transmit voltage boost. Range 0-1
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*/
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void octeon_qlm_tune_v3(int node, int qlm, int baud_mhz, int tx_swing, int tx_premptap, int tx_gain,
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int tx_vboost);
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/**
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* Disables DFE for the specified QLM lane(s).
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* This function should only be called for low-loss channels.
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*
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* @param node Node to configure
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* @param qlm QLM to configure
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* @param lane Lane to configure, or -1 all lanes
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* @param baud_mhz The speed the QLM needs to be configured in Mhz.
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* @param mode The QLM to be configured as SGMII/XAUI/PCIe.
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*/
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void octeon_qlm_dfe_disable(int node, int qlm, int lane, int baud_mhz, int mode);
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/**
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* Some QLMs need to override the default pre-ctle for low loss channels.
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*
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* @param node Node to configure
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* @param qlm QLM to configure
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* @param pre_ctle pre-ctle settings for low loss channels
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*/
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void octeon_qlm_set_channel_v3(int node, int qlm, int pre_ctle);
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void octeon_init_qlm(int node);
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int octeon_mcu_probe(int node);
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#endif /* __OCTEON_QLM_H__ */
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