mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
d25d2db847
Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
139 lines
2.7 KiB
Text
139 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Marvell / Cavium Inc. EVB CN7300
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "mrvl,cn73xx.dtsi"
|
|
|
|
/ {
|
|
model = "cavium,ebb7304";
|
|
compatible = "cavium,ebb7304";
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
spi0 = &spi;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = &uart0;
|
|
};
|
|
};
|
|
|
|
&bootbus {
|
|
/*
|
|
* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
|
|
* as the initial size is too small for the 8MiB flash device
|
|
*/
|
|
ranges = <0 0 0 0x1f400000 0xc00000>,
|
|
<1 0 0x10000 0x10000000 0>,
|
|
<2 0 0x10000 0x20000000 0>,
|
|
<3 0 0x10000 0x30000000 0>,
|
|
<4 0 0 0x1d020000 0x10000>,
|
|
<5 0 0x10000 0x50000000 0>,
|
|
<6 0 0x10000 0x60000000 0>,
|
|
<7 0 0x10000 0x70000000 0>;
|
|
|
|
cavium,cs-config@0 {
|
|
compatible = "cavium,octeon-3860-bootbus-config";
|
|
cavium,cs-index = <0>;
|
|
cavium,t-adr = <10>;
|
|
cavium,t-ce = <50>;
|
|
cavium,t-oe = <50>;
|
|
cavium,t-we = <35>;
|
|
cavium,t-rd-hld = <25>;
|
|
cavium,t-wr-hld = <35>;
|
|
cavium,t-pause = <0>;
|
|
cavium,t-wait = <50>;
|
|
cavium,t-page = <30>;
|
|
cavium,t-rd-dly = <0>;
|
|
cavium,page-mode = <1>;
|
|
cavium,pages = <8>;
|
|
cavium,bus-width = <8>;
|
|
};
|
|
|
|
cavium,cs-config@4 {
|
|
compatible = "cavium,octeon-3860-bootbus-config";
|
|
cavium,cs-index = <4>;
|
|
cavium,t-adr = <10>;
|
|
cavium,t-ce = <10>;
|
|
cavium,t-oe = <160>;
|
|
cavium,t-we = <100>;
|
|
cavium,t-rd-hld = <10>;
|
|
cavium,t-wr-hld = <0>;
|
|
cavium,t-pause = <50>;
|
|
cavium,t-wait = <50>;
|
|
cavium,t-page = <10>;
|
|
cavium,t-rd-dly = <10>;
|
|
cavium,pages = <0>;
|
|
cavium,bus-width = <8>;
|
|
};
|
|
|
|
flash0: nor@0,0 {
|
|
compatible = "cfi-flash";
|
|
reg = <0 0 0x800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "bootloader";
|
|
reg = <0 0x340000>;
|
|
read-only;
|
|
};
|
|
partition@300000 {
|
|
label = "storage";
|
|
reg = <0x340000 0x4be000>;
|
|
};
|
|
partition@7fe000 {
|
|
label = "environment";
|
|
reg = <0x7fe000 0x2000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart0 {
|
|
clock-frequency = <1200000000>;
|
|
};
|
|
|
|
&i2c0 {
|
|
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
&i2c1 {
|
|
u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
&spi {
|
|
flash@0 {
|
|
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
|
spi-max-frequency = <2000000>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
/* USB 0 */
|
|
&usb0 {
|
|
status = "okay";
|
|
/*
|
|
* Power is specified by three parts:
|
|
* 1) GPIO handle (must be &gpio)
|
|
* 2) GPIO pin number
|
|
* 3) Active high (0) or active low (1)
|
|
*/
|
|
power = <&gpio 20 0>;
|
|
};
|
|
|
|
/* USB 1 */
|
|
&usb1 {
|
|
status = "okay";
|
|
/*
|
|
* Power is specified by three parts:
|
|
* 1) GPIO handle (must be &gpio)
|
|
* 2) GPIO pin number
|
|
* 3) Active high (0) or active low (1)
|
|
*/
|
|
power = <&gpio 21 0>;
|
|
};
|