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https://github.com/AsahiLinux/u-boot
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ce9c579e2b
Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org>
142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#ifndef _ASM_ARMV8_MMU_H_
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#define _ASM_ARMV8_MMU_H_
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#include <hang.h>
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#include <linux/const.h>
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/*
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* block/section address mask and size definitions.
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*/
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/* PAGE_SHIFT determines the page size */
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#undef PAGE_SIZE
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE - 1))
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/***************************************************************/
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/*
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* Memory types
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*/
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#define MT_DEVICE_NGNRNE 0
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#define MT_DEVICE_NGNRE 1
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#define MT_DEVICE_GRE 2
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#define MT_NORMAL_NC 3
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#define MT_NORMAL 4
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#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
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(0x04 << (MT_DEVICE_NGNRE * 8)) | \
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(0x0c << (MT_DEVICE_GRE * 8)) | \
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(0x44 << (MT_NORMAL_NC * 8)) | \
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(UL(0xff) << (MT_NORMAL * 8)))
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/*
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* Hardware page table definitions.
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*
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*/
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#define PTE_TYPE_MASK (3 << 0)
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#define PTE_TYPE_FAULT (0 << 0)
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#define PTE_TYPE_TABLE (3 << 0)
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#define PTE_TYPE_PAGE (3 << 0)
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#define PTE_TYPE_BLOCK (1 << 0)
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#define PTE_TYPE_VALID (1 << 0)
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#define PTE_TABLE_PXN (1UL << 59)
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#define PTE_TABLE_XN (1UL << 60)
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#define PTE_TABLE_AP (1UL << 61)
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#define PTE_TABLE_NS (1UL << 63)
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/*
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* Block
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*/
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#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
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#define PTE_BLOCK_NS (1 << 5)
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#define PTE_BLOCK_NON_SHARE (0 << 8)
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#define PTE_BLOCK_OUTER_SHARE (2 << 8)
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#define PTE_BLOCK_INNER_SHARE (3 << 8)
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#define PTE_BLOCK_AF (1 << 10)
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#define PTE_BLOCK_NG (1 << 11)
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#define PTE_BLOCK_PXN (UL(1) << 53)
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#define PTE_BLOCK_UXN (UL(1) << 54)
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/*
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* AttrIndx[2:0]
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*/
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#define PMD_ATTRINDX(t) ((t) << 2)
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#define PMD_ATTRINDX_MASK (7 << 2)
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#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
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PTE_BLOCK_UXN | \
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PMD_ATTRINDX_MASK | \
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PTE_TYPE_VALID)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ(x) ((64 - (x)) << 0)
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#define TCR_IRGN_NC (0 << 8)
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#define TCR_IRGN_WBWA (1 << 8)
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#define TCR_IRGN_WT (2 << 8)
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#define TCR_IRGN_WBNWA (3 << 8)
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#define TCR_IRGN_MASK (3 << 8)
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#define TCR_ORGN_NC (0 << 10)
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#define TCR_ORGN_WBWA (1 << 10)
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#define TCR_ORGN_WT (2 << 10)
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#define TCR_ORGN_WBNWA (3 << 10)
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#define TCR_ORGN_MASK (3 << 10)
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#define TCR_SHARED_NON (0 << 12)
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#define TCR_SHARED_OUTER (2 << 12)
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#define TCR_SHARED_INNER (3 << 12)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_TG0_64K (1 << 14)
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#define TCR_TG0_16K (2 << 14)
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#define TCR_EPD1_DISABLE (1 << 23)
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#define TCR_EL1_RSVD (1U << 31)
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#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
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#define TCR_EL3_RSVD (1U << 31 | 1 << 23)
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#define HCR_EL2_E2H_BIT 34
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#ifndef __ASSEMBLY__
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static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
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{
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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}
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struct mm_region {
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u64 virt;
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u64 phys;
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u64 size;
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u64 attrs;
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};
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extern struct mm_region *mem_map;
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void setup_pgtables(void);
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u64 get_tcr(u64 *pips, u64 *pva_bits);
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#endif
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#endif /* _ASM_ARMV8_MMU_H_ */
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