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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/i8254.h>
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#include <asm/ibmpc.h>
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#include <asm/interrupt.h>
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#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
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#define TIMER2_VALUE 0x0a8e /* 440Hz */
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static int timer_init_done = 0;
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int timer_init(void)
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{
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/* initialize timer 0 and 2
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*
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* Timer 0 is used to increment system_tick 1000 times/sec
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* Timer 1 was used for DRAM refresh in early PC's
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* Timer 2 is used to drive the speaker
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* (to stasrt a beep: write 3 to port 0x61,
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* to stop it again: write 0)
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*/
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outb (PIT_CMD_CTR0 | PIT_CMD_BOTH | PIT_CMD_MODE2,
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PIT_BASE + PIT_COMMAND);
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outb (TIMER0_VALUE & 0xff, PIT_BASE + PIT_T0);
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outb (TIMER0_VALUE >> 8, PIT_BASE + PIT_T0);
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outb (PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
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PIT_BASE + PIT_COMMAND);
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outb (TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
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outb (TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
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irq_install_handler (0, timer_isr, NULL);
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unmask_irq (0);
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timer_init_done = 1;
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return 0;
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}
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static u16 read_pit(void)
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{
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u8 low;
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outb (PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
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low = inb (PIT_BASE + PIT_T0);
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return ((inb (PIT_BASE + PIT_T0) << 8) | low);
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}
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/* this is not very exact */
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void __udelay (unsigned long usec)
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{
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int counter;
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int wraps;
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if (timer_init_done)
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{
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counter = read_pit ();
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wraps = usec / 1000;
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usec = usec % 1000;
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usec *= 1194;
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usec /= 1000;
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usec += counter;
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while (usec > 1194) {
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usec -= 1194;
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wraps++;
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}
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while (1) {
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int new_count = read_pit ();
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if (((new_count < usec) && !wraps) || wraps < 0)
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break;
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if (new_count > counter)
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wraps--;
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counter = new_count;
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}
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}
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}
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