mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 17:41:08 +00:00
7205e4075d
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
226 lines
8.3 KiB
C
226 lines
8.3 KiB
C
/******************************************************************************
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* A collection of structures, addresses, and values associated with
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* the Motorola 850T AdderIIF board. Copied from the FADS stuff.
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*******************************************************************************
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* 2003-JUL: The AdderII is using the following physical memorymap:
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*******************************************************************************
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* FA200000 -> FA20FFFF : IMAP internal in the cpu
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* FE000000 -> FE400000 : flash connected to CS0, setup by 8xxrom
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* 00000000 -> 00800000 : sdram setup by 8xxrom
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*******************************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <mpc8xx_irq.h>
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_ADDERII 1
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/* CPU Clock speed */
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#define MPC8XX_FACT 12 /* Multilpy by 12 */
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#define MPC8XX_XIN 4000000 /* 4MHz */
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#define MPC8XX_HZ ( MPC8XX_FACT * MPC8XX_XIN )
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
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#define CONFIG_SDRAM_50MHZ 1
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/* Default Serial Console, baudrate */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_LOADS_ECHO 1
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/* FEC Ethernet controller configurations */
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#define CONFIG_FEC_ETH 1
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#define CONFIG_NET_MULTI 1
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#define FEC_ENET 1
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL3 /* FEC interrupt */
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/* Older kernels need clock in MHz newer in Hz */
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#define CONFIG_CLOCKS_IN_MHZ 1
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/* Monitor Functions */
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#define CONFIG_COMMANDS ( CFG_CMD_ENV | \
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CFG_CMD_FLASH | \
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CFG_CMD_MEMORY| \
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CFG_CMD_NET | \
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CFG_CMD_PING | \
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CFG_CMD_SDRAM )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/* Configuration Settings */
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
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#define CFG_CBSIZE 1024 /* Console I/P buffer size */
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#else
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#define CFG_CBSIZE 256
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#endif
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#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
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/* Print buffer size */
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#define CFG_MAXARGS 16 /* Max number of cmd args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot args buffer size */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_MEMTEST_START 0x00100000 /* Mem test works on */
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#define CFG_MEMTEST_END 0x00800000 /* 1 ... 8MB in SDRAM */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000
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/******************************************************************************
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** Low level configuration settings.
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** ( adderss mappings, register init values, etc. )
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** You should know what you are doing if you make changes here.
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******************************************************************************/
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/* Start address for the final memory configuration set up by startup code
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** Please note that CFG_SDRAM_BASE must start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_SIZE (( uint ) ( 4 * 1024 * 1024 )) /* 4MB */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN ( 256 << 10 ) /* 256 KByte */
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#define CFG_MALLOC_LEN ( 384 << 10 ) /* 384 KByte SDRAM rsvd */
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/* malloc() usage */
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/**
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** For booting Linux, the board info and command line data
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** have to be in the first 8 MB of memory, since this is
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** the maximum mapped by the Linux kernel during initialization.
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**/
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#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
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/******************************************************************************
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** Flash Organization
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******************************************************************************/
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#define CFG_MAX_FLASH_BANKS 1 /* Max no of flash mem banks */
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#define CFG_MAX_FLASH_SECT 71 /* Max no of sec on 1 chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Erase flash timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Write flash timeout (ms) */
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/******************************************************************************
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** U-BOOT Environment variables in Flash
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******************************************************************************/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00040000
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#define CFG_ENV_SIZE 0x10000 /* 64KBytes env space */
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#define CFG_ENV_SECT_SIZE 0x10000
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/******************************************************************************
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** Cache Configuration
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******************************************************************************/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/******************************************************************************
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** Internal memory mapped register
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******************************************************************************/
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#define CFG_IMMR 0xFA200000
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#define CFG_IMMR_SIZE (( uint) ( 62 * 1024 )) /* 64 KByte res */
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/* Definitions for initial stack pointer and data area ( in DPRAM ) */
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* end of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64
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#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* SIU Module Configuration Register */
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#define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
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/******************************************************************************
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** SYPCR - System protection and control
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** SYPCR - can be written only once after reset
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******************************************************************************/
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#if defined( CONFIG_WATCHDOG )
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#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
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SYPCR_SWP )
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#else
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#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWP )
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#endif
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/* TBSCR - Time Base Status and Control Register */
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#define CFG_TBSCR ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBE )
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/* PISCR - Periodic Interrupt Status and Control */
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#define CFG_PISCR ( PISCR_PS | PISCR_PITF )
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/* PLPRCR - PLL, Low-Power, and Reset Control Register */
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#define CFG_PLPRCR ((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
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/* SCCR - System Clock and reset Control Register */
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR ( SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000| SCCR_DFNH000 | \
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SCCR_DFLCD000 | SCCR_DFALCD00 )
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#define CFG_DER 0
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/******************************************************************************
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** Because of the way the 860 starts up and assigns CS0 the
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** entire address space, we have to set the memory controller
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** differently. Normally, you write the option register
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** first, and then enable the chip select by writing the
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** base register. For CS0, you must write the base register
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** first, followed by the option register.
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******************************************************************************/
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/**
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** Memory Controller Definitions
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** BR0/1/2... and OR0/1/2...
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*/
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/* For AdderII BR0 FLASH */
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#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
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/* Flash Timings: ACS = 11, TRLX = 1, CSNT = 0, SCY = 7 */
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#define CFG_OR_TIMING_FLASH ( OR_ACS_DIV2 | OR_BI | OR_SCY_7_CLK | OR_TRLX )
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#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH )
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#define CFG_OR0_PRELIM CFG_OR0_REMAP
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#define CFG_BR0_PRELIM (( CFG_FLASH_BASE & BR_BA_MSK ) | \
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BR_PS_16 | BR_V )
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/* For AdderII BR1 SDRAM */
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#define CFG_PRELIM_OR1_AM 0xFF800000
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#define CFG_OR1_REMAP ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
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#define CFG_OR1_PRELIM ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
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#define CFG_BR1_PRELIM ( CFG_SDRAM_BASE | BR_MS_UPMA | BR_V )
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/*******************************************************************************
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* Internal Definitions Boot Flags
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*******************************************************************************/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif
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/* __CONFIG_H */
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