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Use prompt instead of code-block to have copy-paste friendly command documentation. Signed-off-by: Nishanth Menon <nm@ti.com>
345 lines
8.2 KiB
ReStructuredText
345 lines
8.2 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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.. sectionauthor:: Manorit Chawdhry <m-chawdhry@ti.com>
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J721S2 and AM68 Platforms
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=========================
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Introduction:
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-------------
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The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
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targeting automotive applications. They are designed as a low power, high
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performance and highly integrated device architecture, adding significant
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enhancement on processing power, graphics capability, video and imaging
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processing, virtualization and coherent memory support.
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The AM68 Starter Kit/Evaluation Module (EVM) is based on the J721S2 family
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of SoCs. They are designed for machine vision, traffic monitoring, retail
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automation, and factory automation.
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The device is partitioned into three functional domains, each containing
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specific processing cores and peripherals:
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1. Wake-up (WKUP) domain:
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* ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
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2. Microcontroller (MCU) domain:
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* Dual core ARM Cortex-R5F processor, runs device management
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and SoC early boot
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3. MAIN domain:
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* Dual core 64-bit ARM Cortex-A72, runs HLOS
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More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28
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Platform information:
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* https://www.ti.com/tool/J721S2XSOMXEVM
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* https://www.ti.com/tool/SK-AM68
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Boot Flow:
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----------
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Below is the pictorial representation of boot flow:
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.. image:: img/boot_diagram_k3_current.svg
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- On this platform, "TI Foundational Security" (TIFS) functions as the
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security enclave master while "Device Manager" (DM), also known as the
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"TISCI server" in TI terminology, offers all the essential services.
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- As illustrated in the diagram above, R5 SPL manages power and clock
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services independently before handing over control to "DM". The A72 or
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the C7x (Aux core) software components request TIFS/DM to handle
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security or device management services.
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Sources:
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--------
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_boot_sources
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:end-before: .. k3_rst_include_end_boot_sources
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Build procedure:
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----------------
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0. Setup the environment variables:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_common_env_vars_desc
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:end-before: .. k3_rst_include_end_common_env_vars_desc
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_board_env_vars_desc
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:end-before: .. k3_rst_include_end_board_env_vars_desc
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Set the variables corresponding to this platform:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_common_env_vars_defn
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:end-before: .. k3_rst_include_end_common_env_vars_defn
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.. prompt:: bash $
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export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
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export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
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export TFA_BOARD=generic
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export TFA_EXTRA_ARGS="K3_USART=0x8"
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# The following is not a typo, j784s4 is the OP-TEE platform for j721s2
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export OPTEE_PLATFORM=k3-j784s4
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export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
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.. j721s2_evm_rst_include_start_build_steps
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1. Trusted Firmware-A:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_tfa
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:end-before: .. k3_rst_include_end_build_steps_tfa
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2. OP-TEE:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_optee
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:end-before: .. k3_rst_include_end_build_steps_optee
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3. U-Boot:
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.. _j721s2_evm_rst_u_boot_r5:
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* 3.1 R5:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_spl_r5
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:end-before: .. k3_rst_include_end_build_steps_spl_r5
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.. _j721s2_evm_rst_u_boot_a72:
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* 3.2 A72:
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_build_steps_uboot
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:end-before: .. k3_rst_include_end_build_steps_uboot
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.. j721s2_evm_rst_include_end_build_steps
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Target Images
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-------------
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In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
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variant (GP, HS-FS, HS-SE) requires a different source for these files.
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- GP
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* tiboot3-j721s2-gp-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
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* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
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- HS-FS
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* tiboot3-j721s2-hs-fs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
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* tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
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- HS-SE
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* tiboot3-j721s2-hs-evm.bin from :ref:`step 3.1 <j721s2_evm_rst_u_boot_r5>`
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* tispl.bin, u-boot.img from :ref:`step 3.2 <j721s2_evm_rst_u_boot_a72>`
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Image formats:
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--------------
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- tiboot3.bin
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.. image:: img/multi_cert_tiboot3.bin.svg
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- tispl.bin
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.. image:: img/dm_tispl.bin.svg
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R5 Memory Map:
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--------------
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.. list-table::
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:widths: 16 16 16
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:header-rows: 1
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* - Region
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- Start Address
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- End Address
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* - SPL
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- 0x41c00000
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- 0x41c40000
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* - EMPTY
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- 0x41c40000
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- 0x41c61f20
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* - STACK
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- 0x41c65f20
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- 0x41c61f20
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* - Global data
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- 0x41c65f20
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- 0x41c66000
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* - Heap
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- 0x41c66000
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- 0x41c76000
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* - BSS
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- 0x41c76000
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- 0x41c80000
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* - DM DATA
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- 0x41c80000
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- 0x41c84130
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* - EMPTY
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- 0x41c84130
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- 0x41cff9fc
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* - MCU Scratchpad
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- 0x41cff9fc
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- 0x41cffbfc
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* - ROM DATA
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- 0x41cffbfc
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- 0x41cfffff
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Switch Setting for Boot Mode
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----------------------------
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Boot Mode pins provide means to select the boot mode and options before the
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device is powered up. After every POR, they are the main source to populate
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the Boot Parameter Tables.
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Boot Mode Pins for J721S2-EVM
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following table shows some common boot modes used on J721S2 platform.
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More details can be found in the Technical Reference Manual:
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https://www.ti.com/lit/pdf/spruj28 under the `Boot Mode Pins` section.
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.. list-table:: Boot Modes
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:widths: 16 16 16
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:header-rows: 1
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* - Switch Label
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- SW9: 12345678
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- SW8: 12345678
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* - SD
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- 00000000
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- 10000010
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* - EMMC
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- 01000000
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- 10000000
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* - OSPI
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- 01000000
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- 00000110
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* - UART
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- 01110000
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- 00000000
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* - USB DFU
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- 00100000
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- 10000000
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For SW8 and SW9, the switch state in the "ON" position = 1.
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Boot Mode Pins for SK-AM68
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following table shows some common boot modes used on AM68-SK platform.
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More details can be found in the User Guide for AM68-SK:
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https://www.ti.com/lit/pdf/spruj68 under the `Bootmode Settings` section.
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.. list-table:: Boot Modes
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:widths: 16 16
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:header-rows: 1
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* - Switch Label
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- SW1: 1234
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* - SD
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- 0000
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* - xSPI
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- 0010
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* - UART
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- 1010
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* - Ethernet
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- 0100
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For SW1, the switch state in the "ON" position = 1.
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Debugging U-Boot
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----------------
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See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
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detailed setup information.
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.. warning::
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**OpenOCD support since**: v0.12.0
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If the default package version of OpenOCD in your development
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environment's distribution needs to be updated, it might be necessary to
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build OpenOCD from the source.
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Debugging U-Boot on J721S2-EVM
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_openocd_connect_XDS110
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:end-before: .. k3_rst_include_end_openocd_connect_XDS110
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To start OpenOCD and connect to the board
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.. prompt:: bash $
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openocd -f board/ti_j721s2evm.cfg
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Debugging U-Boot on SK-AM68
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_openocd_connect_cti20
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:end-before: .. k3_rst_include_end_openocd_connect_cti20
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_openocd_cfg_external_intro
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:end-before: .. k3_rst_include_end_openocd_cfg_external_intro
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For SK-AM68, the openocd_connect.cfg is as follows:
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.. code-block:: tcl
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# TUMPA example:
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# http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
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source [find interface/ftdi/tumpa.cfg]
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transport select jtag
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# default JTAG configuration has only SRST and no TRST
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reset_config srst_only srst_push_pull
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# delay after SRST goes inactive
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adapter srst delay 20
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if { ![info exists SOC] } {
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# Set the SoC of interest
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set SOC j721s2
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}
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source [find target/ti_k3.cfg]
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ftdi tdo_sample_edge falling
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# Speeds for FT2232H are in multiples of 2, and 32MHz is tops
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# max speed we seem to achieve is ~20MHz.. so we pick 16MHz
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adapter speed 16000
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