u-boot/arch/riscv/lib/cache.c
Lukas Auer f74c416e62 riscv: use invalidate/flush_*cache_range functions in cache.c
The flush_cache() function in lib/cache.c ignores its arguments and
flushes the complete data and instruction caches. Use the
invalidate/flush_*cache_range() functions instead to only flush the
requested memory region.

This patch does not change the current behavior of U-Boot, since the
implementation of the invalidate/flush_*cache_range() functions flush
the complete data and instruction caches. It is in preparation for CPUs
with the necessary functionality for flushing a selectable memory range.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-15 09:36:31 +08:00

71 lines
1.1 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <common.h>
void invalidate_icache_all(void)
{
asm volatile ("fence.i" ::: "memory");
}
__weak void flush_dcache_all(void)
{
}
__weak void flush_dcache_range(unsigned long start, unsigned long end)
{
}
void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
* instruction cache. Invalidate all of it instead.
*/
invalidate_icache_all();
}
__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
{
}
void cache_flush(void)
{
invalidate_icache_all();
flush_dcache_all();
}
void flush_cache(unsigned long addr, unsigned long size)
{
invalidate_icache_range(addr, addr + size);
flush_dcache_range(addr, addr + size);
}
__weak void icache_enable(void)
{
}
__weak void icache_disable(void)
{
}
__weak int icache_status(void)
{
return 0;
}
__weak void dcache_enable(void)
{
}
__weak void dcache_disable(void)
{
}
__weak int dcache_status(void)
{
return 0;
}