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https://github.com/AsahiLinux/u-boot
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37a4b75d4c
Rather than only support the pins dedicated as chip selects, utilize the gpio framework to support any gpio pin. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
302 lines
6.5 KiB
C
302 lines
6.5 KiB
C
/*
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* Driver for Blackfin On-Chip SPI device
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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/*#define DEBUG*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/blackfin.h>
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#include <asm/gpio.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/spi.h>
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struct bfin_spi_slave {
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struct spi_slave slave;
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void *mmr_base;
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u16 ctl, baud, flg;
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};
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#define MAKE_SPI_FUNC(mmr, off) \
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static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
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static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
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MAKE_SPI_FUNC(SPI_CTL, 0x00)
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MAKE_SPI_FUNC(SPI_FLG, 0x04)
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MAKE_SPI_FUNC(SPI_STAT, 0x08)
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MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
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MAKE_SPI_FUNC(SPI_RDBR, 0x10)
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MAKE_SPI_FUNC(SPI_BAUD, 0x14)
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#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
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#define MAX_CTRL_CS 7
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#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
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#ifdef CONFIG_BFIN_SPI_GPIO_CS
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# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
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#else
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# define is_gpio_cs(cs) 0
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#endif
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (is_gpio_cs(cs))
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return gpio_is_valid(gpio_cs(cs));
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else
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return (cs >= 1 && cs <= MAX_CTRL_CS);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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if (is_gpio_cs(slave->cs)) {
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unsigned int cs = gpio_cs(slave->cs);
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gpio_set_value(cs, bss->flg);
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debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
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} else {
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write_SPI_FLG(bss,
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(read_SPI_FLG(bss) &
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~((!bss->flg << 8) << slave->cs)) |
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(1 << slave->cs));
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debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
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}
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SSYNC();
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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if (is_gpio_cs(slave->cs)) {
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unsigned int cs = gpio_cs(slave->cs);
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gpio_set_value(cs, !bss->flg);
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debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
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} else {
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u16 flg;
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/* make sure we force the cs to deassert rather than let the
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* pin float back up. otherwise, exact timings may not be
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* met some of the time leading to random behavior (ugh).
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*/
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flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
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write_SPI_FLG(bss, flg);
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SSYNC();
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debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
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flg &= ~(1 << slave->cs);
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write_SPI_FLG(bss, flg);
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debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
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}
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SSYNC();
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}
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void spi_init()
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{
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}
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#ifdef SPI_CTL
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# define SPI0_CTL SPI_CTL
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#endif
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#define SPI_PINS(n) \
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[n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
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static unsigned short pins[][5] = {
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#ifdef SPI0_CTL
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SPI_PINS(0),
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#endif
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#ifdef SPI1_CTL
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SPI_PINS(1),
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#endif
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#ifdef SPI2_CTL
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SPI_PINS(2),
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#endif
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};
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#define SPI_CS_PINS(n) \
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[n] = { \
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P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
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P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
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P_SPI##n##_SSEL7, \
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}
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static const unsigned short cs_pins[][7] = {
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#ifdef SPI0_CTL
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SPI_CS_PINS(0),
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#endif
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#ifdef SPI1_CTL
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SPI_CS_PINS(1),
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#endif
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#ifdef SPI2_CTL
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SPI_CS_PINS(2),
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#endif
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};
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct bfin_spi_slave *bss;
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ulong sclk;
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u32 mmr_base;
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u32 baud;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
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debug("%s: invalid bus %u\n", __func__, bus);
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return NULL;
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}
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switch (bus) {
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#ifdef SPI0_CTL
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case 0: mmr_base = SPI0_CTL; break;
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#endif
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#ifdef SPI1_CTL
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case 1: mmr_base = SPI1_CTL; break;
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#endif
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#ifdef SPI2_CTL
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case 2: mmr_base = SPI2_CTL; break;
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#endif
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default: return NULL;
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}
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sclk = get_sclk();
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baud = sclk / (2 * max_hz);
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/* baud should be rounded up */
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if (sclk % (2 * max_hz))
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baud += 1;
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if (baud < 2)
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baud = 2;
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else if (baud > (u16)-1)
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baud = -1;
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bss = malloc(sizeof(*bss));
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if (!bss)
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return NULL;
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bss->slave.bus = bus;
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bss->slave.cs = cs;
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bss->mmr_base = (void *)mmr_base;
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bss->ctl = SPE | MSTR | TDBR_CORE;
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if (mode & SPI_CPHA) bss->ctl |= CPHA;
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if (mode & SPI_CPOL) bss->ctl |= CPOL;
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if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
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bss->baud = baud;
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bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
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debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
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bus, cs, mmr_base, bss->ctl, baud, bss->flg);
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return &bss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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free(bss);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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if (is_gpio_cs(slave->cs)) {
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unsigned int cs = gpio_cs(slave->cs);
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gpio_request(cs, "bfin-spi");
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gpio_direction_output(cs, !bss->flg);
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pins[slave->bus][0] = P_DONTCARE;
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} else
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pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
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peripheral_request_list(pins[slave->bus], "bfin-spi");
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write_SPI_CTL(bss, bss->ctl);
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write_SPI_BAUD(bss, bss->baud);
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SSYNC();
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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peripheral_free_list(pins[slave->bus]);
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if (is_gpio_cs(slave->cs))
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gpio_free(gpio_cs(slave->cs));
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write_SPI_CTL(bss, 0);
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SSYNC();
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}
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#ifndef CONFIG_BFIN_SPI_IDLE_VAL
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# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
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#endif
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
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const u8 *tx = dout;
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u8 *rx = din;
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uint bytes = bitlen / 8;
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int ret = 0;
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
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slave->bus, slave->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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goto done;
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/* we can only do 8 bit transfers */
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if (bitlen % 8) {
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flags |= SPI_XFER_END;
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goto done;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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/* todo: take advantage of hardware fifos and setup RX dma */
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while (bytes--) {
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u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
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debug("%s: tx:%x ", __func__, value);
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write_SPI_TDBR(bss, value);
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SSYNC();
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while ((read_SPI_STAT(bss) & TXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & SPIF))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & RXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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value = read_SPI_RDBR(bss);
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if (rx)
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*rx++ = value;
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debug("rx:%x\n", value);
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}
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done:
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return ret;
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}
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