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https://github.com/AsahiLinux/u-boot
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e19441ecbc
Add support for display and bits-per-pixel properties. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
432 lines
10 KiB
C
432 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX23/i.MX28 LCDIF driver
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*
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* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/errno.h>
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#include <malloc.h>
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#include <video.h>
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#include <video_fb.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/dma.h>
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#include <asm/io.h>
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#include "videomodes.h"
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#define PS2KHZ(ps) (1000000000UL / (ps))
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#define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
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#define BITS_PP 18
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#define BYTES_PP 4
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struct mxs_dma_desc desc;
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/**
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* mxsfb_system_setup() - Fine-tune LCDIF configuration
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*
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* This function is used to adjust the LCDIF configuration. This is usually
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* needed when driving the controller in System-Mode to operate an 8080 or
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* 6800 connected SmartLCD.
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*/
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__weak void mxsfb_system_setup(void)
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{
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}
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/*
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* ARIES M28EVK:
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* setenv videomode
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* video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
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* le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
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*
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* Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
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* setenv videomode
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* video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
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* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
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*/
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static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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uint32_t word_len = 0, bus_width = 0;
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uint8_t valid_data = 0;
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/* Kick in the LCDIF clock */
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mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
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/* Restart the LCDIF block */
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mxs_reset_block(®s->hw_lcdif_ctrl_reg);
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switch (bpp) {
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case 24:
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word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
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bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
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valid_data = 0x7;
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break;
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case 18:
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word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
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bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
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valid_data = 0x7;
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break;
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case 16:
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word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
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bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
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valid_data = 0xf;
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break;
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case 8:
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word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
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bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
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valid_data = 0xf;
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break;
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}
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writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
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®s->hw_lcdif_ctrl);
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writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
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®s->hw_lcdif_ctrl1);
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mxsfb_system_setup();
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writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
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LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
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LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
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mode->vsync_len, ®s->hw_lcdif_vdctrl0);
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writel(mode->upper_margin + mode->lower_margin +
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mode->vsync_len + mode->yres,
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®s->hw_lcdif_vdctrl1);
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writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
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(mode->left_margin + mode->right_margin +
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mode->hsync_len + mode->xres),
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®s->hw_lcdif_vdctrl2);
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writel(((mode->left_margin + mode->hsync_len) <<
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LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
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(mode->upper_margin + mode->vsync_len),
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®s->hw_lcdif_vdctrl3);
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writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
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®s->hw_lcdif_vdctrl4);
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writel(fb_addr, ®s->hw_lcdif_cur_buf);
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writel(fb_addr, ®s->hw_lcdif_next_buf);
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/* Flush FIFO first */
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writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
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#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
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/* Sync signals ON */
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setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
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#endif
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/* FIFO cleared */
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writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
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/* RUN! */
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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}
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static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
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{
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/* Start framebuffer */
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mxs_lcd_init(fb, mode, bpp);
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#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
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/*
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* If the LCD runs in system mode, the LCD refresh has to be triggered
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* manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
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* having to set this bit manually after every single change in the
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* framebuffer memory, we set up specially crafted circular DMA, which
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* sets the RUN bit, then waits until it gets cleared and repeats this
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* infinitelly. This way, we get smooth continuous updates of the LCD.
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*/
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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memset(&desc, 0, sizeof(struct mxs_dma_desc));
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desc.address = (dma_addr_t)&desc;
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desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
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MXS_DMA_DESC_WAIT4END |
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(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
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desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
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desc.cmd.next = (uint32_t)&desc.cmd;
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/* Execute the DMA chain. */
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mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
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#endif
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return 0;
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}
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static int mxs_remove_common(u32 fb)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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int timeout = 1000000;
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if (!fb)
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return -EINVAL;
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writel(fb, ®s->hw_lcdif_cur_buf_reg);
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writel(fb, ®s->hw_lcdif_next_buf_reg);
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writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
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while (--timeout) {
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if (readl(®s->hw_lcdif_ctrl1_reg) &
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LCDIF_CTRL1_VSYNC_EDGE_IRQ)
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break;
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udelay(1);
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}
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mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
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return 0;
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}
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#ifndef CONFIG_DM_VIDEO
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static GraphicDevice panel;
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void lcdif_power_down(void)
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{
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mxs_remove_common(panel.frameAdrs);
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}
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void *video_hw_init(void)
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{
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int bpp = -1;
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int ret = 0;
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char *penv;
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void *fb = NULL;
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struct ctfb_res_modes mode;
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puts("Video: ");
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/* Suck display configuration from "videomode" variable */
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penv = env_get("videomode");
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if (!penv) {
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puts("MXSFB: 'videomode' variable not set!\n");
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return NULL;
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}
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bpp = video_get_params(&mode, penv);
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/* fill in Graphic device struct */
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sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
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panel.winSizeX = mode.xres;
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panel.winSizeY = mode.yres;
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panel.plnSizeX = mode.xres;
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panel.plnSizeY = mode.yres;
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switch (bpp) {
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case 24:
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case 18:
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panel.gdfBytesPP = 4;
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panel.gdfIndex = GDF_32BIT_X888RGB;
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break;
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case 16:
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panel.gdfBytesPP = 2;
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panel.gdfIndex = GDF_16BIT_565RGB;
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break;
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case 8:
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panel.gdfBytesPP = 1;
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panel.gdfIndex = GDF__8BIT_INDEX;
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break;
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default:
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printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
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return NULL;
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}
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panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
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/* Allocate framebuffer */
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fb = memalign(ARCH_DMA_MINALIGN,
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roundup(panel.memSize, ARCH_DMA_MINALIGN));
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if (!fb) {
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printf("MXSFB: Error allocating framebuffer!\n");
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return NULL;
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}
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/* Wipe framebuffer */
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memset(fb, 0, panel.memSize);
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panel.frameAdrs = (u32)fb;
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printf("%s\n", panel.modeIdent);
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ret = mxs_probe_common(&mode, bpp, (u32)fb);
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if (ret)
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goto dealloc_fb;
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return (void *)&panel;
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dealloc_fb:
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free(fb);
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return NULL;
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}
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#else /* ifndef CONFIG_DM_VIDEO */
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static int mxs_of_get_timings(struct udevice *dev,
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struct display_timing *timings,
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u32 *bpp)
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{
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int ret = 0;
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u32 display_phandle;
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ofnode display_node;
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ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
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if (ret) {
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dev_err(dev, "required display property isn't provided\n");
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return -EINVAL;
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}
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display_node = ofnode_get_by_phandle(display_phandle);
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if (!ofnode_valid(display_node)) {
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dev_err(dev, "failed to find display subnode\n");
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return -EINVAL;
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}
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ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
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if (ret) {
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dev_err(dev,
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"required bits-per-pixel property isn't provided\n");
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return -EINVAL;
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}
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ret = ofnode_decode_display_timing(display_node, 0, timings);
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if (ret) {
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dev_err(dev, "failed to get any display timings\n");
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return -EINVAL;
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}
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return ret;
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}
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static int mxs_video_probe(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ctfb_res_modes mode;
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struct display_timing timings;
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u32 bpp = 0;
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u32 fb_start, fb_end;
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int ret;
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debug("%s() plat: base 0x%lx, size 0x%x\n",
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__func__, plat->base, plat->size);
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ret = mxs_of_get_timings(dev, &timings, &bpp);
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if (ret)
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return ret;
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mode.xres = timings.hactive.typ;
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mode.yres = timings.vactive.typ;
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mode.left_margin = timings.hback_porch.typ;
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mode.right_margin = timings.hfront_porch.typ;
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mode.upper_margin = timings.vback_porch.typ;
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mode.lower_margin = timings.vfront_porch.typ;
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mode.hsync_len = timings.hsync_len.typ;
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mode.vsync_len = timings.vsync_len.typ;
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mode.pixclock = HZ2PS(timings.pixelclock.typ);
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ret = mxs_probe_common(&mode, bpp, plat->base);
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if (ret)
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return ret;
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switch (bpp) {
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case 32:
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case 24:
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case 18:
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uc_priv->bpix = VIDEO_BPP32;
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break;
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case 16:
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uc_priv->bpix = VIDEO_BPP16;
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break;
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case 8:
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uc_priv->bpix = VIDEO_BPP8;
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break;
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default:
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dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
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return -EINVAL;
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}
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uc_priv->xsize = mode.xres;
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uc_priv->ysize = mode.yres;
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/* Enable dcache for the frame buffer */
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fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
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fb_end = plat->base + plat->size;
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fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
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mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
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DCACHE_WRITEBACK);
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video_set_flush_dcache(dev, true);
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return ret;
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}
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static int mxs_video_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct display_timing timings;
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u32 bpp = 0;
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u32 bytes_pp = 0;
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int ret;
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ret = mxs_of_get_timings(dev, &timings, &bpp);
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if (ret)
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return ret;
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switch (bpp) {
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case 32:
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case 24:
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case 18:
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bytes_pp = 4;
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break;
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case 16:
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bytes_pp = 2;
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break;
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case 8:
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bytes_pp = 1;
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break;
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default:
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dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
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return -EINVAL;
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}
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plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
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return 0;
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}
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static int mxs_video_remove(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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mxs_remove_common(plat->base);
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return 0;
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}
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static const struct udevice_id mxs_video_ids[] = {
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{ .compatible = "fsl,imx23-lcdif" },
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{ .compatible = "fsl,imx28-lcdif" },
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{ .compatible = "fsl,imx7ulp-lcdif" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(mxs_video) = {
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.name = "mxs_video",
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.id = UCLASS_VIDEO,
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.of_match = mxs_video_ids,
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.bind = mxs_video_bind,
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.probe = mxs_video_probe,
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.remove = mxs_video_remove,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif /* ifndef CONFIG_DM_VIDEO */
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