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dd38374d2f
This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
641 lines
15 KiB
C
641 lines
15 KiB
C
/*
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
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* Copyright (C) 2015 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include "../init.h"
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#include "../soc-info.h"
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#include "ddrmphy-regs.h"
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#include "umc-regs.h"
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#define DRAM_CH_NR 3
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enum dram_freq {
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DRAM_FREQ_1866M,
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DRAM_FREQ_2133M,
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DRAM_FREQ_NR,
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};
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enum dram_size {
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DRAM_SZ_256M,
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DRAM_SZ_512M,
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DRAM_SZ_NR,
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};
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/* PHY */
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static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
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static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
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static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
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static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
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static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
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static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
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static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
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static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
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static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
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static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
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static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
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/* dependent on package and board design */
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static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
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/* DDR multiPHY */
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static inline int ddrphy_get_rank(int dx)
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{
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return dx / 2;
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}
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static void ddrphy_fifo_reset(void __iomem *phy_base)
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{
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u32 tmp;
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tmp = readl(phy_base + MPHY_PGCR0);
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tmp &= ~MPHY_PGCR0_PHYFRST;
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writel(tmp, phy_base + MPHY_PGCR0);
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udelay(1);
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tmp |= MPHY_PGCR0_PHYFRST;
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writel(tmp, phy_base + MPHY_PGCR0);
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udelay(1);
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}
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static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
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{
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u32 tmp;
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tmp = readl(phy_base + MPHY_PGCR1);
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if (enable)
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tmp &= ~MPHY_PGCR1_INHVT;
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else
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tmp |= MPHY_PGCR1_INHVT;
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writel(tmp, phy_base + MPHY_PGCR1);
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if (!enable) {
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while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))
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cpu_relax();
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}
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}
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static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
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{
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int dx;
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u32 lcdlr1, rdqsd;
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void __iomem *dx_base = phy_base + MPHY_DX_BASE;
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ddrphy_vt_ctrl(phy_base, 0);
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for (dx = 0; dx < nr_dx; dx++) {
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lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1);
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rdqsd = (lcdlr1 >> 8) & 0xff;
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rdqsd = clamp(rdqsd + step, 0U, 0xffU);
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lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
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writel(lcdlr1, dx_base + MPHY_DX_LCDLR1);
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readl(dx_base + MPHY_DX_LCDLR1); /* relax */
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dx_base += MPHY_DX_STRIDE;
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}
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ddrphy_vt_ctrl(phy_base, 1);
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}
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static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
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{
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void __iomem *dx_base = phy_base + MPHY_DX_BASE;
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const int nr_dx = width / 8;
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int dx, rank;
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u32 gtr;
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int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
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for (dx = 0; dx < nr_dx; dx++) {
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gtr = readl(dx_base + MPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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dgsl = gtr & 0x7;
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/* if dgsl is zero, this rank was not trained. skip. */
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if (dgsl) {
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dgsl_min = min(dgsl_min, dgsl);
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dgsl_max = max(dgsl_max, dgsl);
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}
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gtr >>= 3;
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}
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dx_base += MPHY_DX_STRIDE;
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}
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if (dgsl_min != dgsl_max)
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printf("DQS Gateing System Latencies are not all leveled.\n");
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return dgsl_max;
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}
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static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
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int ch)
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{
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u32 tmp;
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void __iomem *zq_base, *dx_base;
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int zq, dx;
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int nr_dx;
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nr_dx = width / 8;
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writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR);
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/*
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* Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
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* to avoid read error issue.
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*/
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writel(0x07d81e37, phy_base + MPHY_PGCR0);
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writel(0x0200c4e0, phy_base + MPHY_PGCR1);
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tmp = ddrphy_pgcr2[freq];
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if (width >= 32)
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tmp |= MPHY_PGCR2_DUALCHN | MPHY_PGCR2_ACPDDC;
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writel(tmp, phy_base + MPHY_PGCR2);
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writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);
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writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);
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writel(0x00083def, phy_base + MPHY_PTR2);
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writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);
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writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);
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writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);
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writel(0x55555555, phy_base + MPHY_ACIOCR1);
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writel(0x00000000, phy_base + MPHY_ACIOCR2);
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writel(0x55555555, phy_base + MPHY_ACIOCR3);
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writel(0x00000000, phy_base + MPHY_ACIOCR4);
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writel(0x00000055, phy_base + MPHY_ACIOCR5);
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writel(0x00181aa4, phy_base + MPHY_DXCCR);
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writel(0x0024641e, phy_base + MPHY_DSGCR);
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writel(0x0000040b, phy_base + MPHY_DCR);
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writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);
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writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);
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writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);
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writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);
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writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);
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writel(0x00000006, phy_base + MPHY_MR1);
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writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);
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writel(0x00000000, phy_base + MPHY_MR3);
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tmp = 0;
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for (dx = 0; dx < nr_dx; dx++)
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tmp |= BIT(MPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
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writel(0x90003087 | tmp, phy_base + MPHY_DTCR);
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writel(0x00000000, phy_base + MPHY_DTAR0);
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writel(0x00000008, phy_base + MPHY_DTAR1);
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writel(0x00000010, phy_base + MPHY_DTAR2);
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writel(0x00000018, phy_base + MPHY_DTAR3);
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writel(0xdd22ee11, phy_base + MPHY_DTDR0);
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writel(0x7788bb44, phy_base + MPHY_DTDR1);
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/* impedance control settings */
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writel(0x04048900, phy_base + MPHY_ZQCR);
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zq_base = phy_base + MPHY_ZQ_BASE;
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for (zq = 0; zq < 4; zq++) {
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/*
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* board-dependent
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* PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
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*/
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writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);
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zq_base += MPHY_ZQ_STRIDE;
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}
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/* DATX8 settings */
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dx_base = phy_base + MPHY_DX_BASE;
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for (dx = 0; dx < 4; dx++) {
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tmp = readl(dx_base + MPHY_DX_GCR0);
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tmp &= ~MPHY_DX_GCR0_WLRKEN_MASK;
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tmp |= BIT(MPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
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MPHY_DX_GCR0_WLRKEN_MASK;
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writel(tmp, dx_base + MPHY_DX_GCR0);
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writel(0x00000000, dx_base + MPHY_DX_GCR1);
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writel(0x00000000, dx_base + MPHY_DX_GCR2);
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writel(0x00000000, dx_base + MPHY_DX_GCR3);
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dx_base += MPHY_DX_STRIDE;
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}
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while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))
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cpu_relax();
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ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
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}
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struct ddrphy_init_sequence {
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char *description;
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u32 init_flag;
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u32 done_flag;
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u32 err_flag;
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};
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static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
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{
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"Impedance Calibration",
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MPHY_PIR_ZCAL,
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MPHY_PGSR0_ZCDONE,
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MPHY_PGSR0_ZCERR,
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},
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{ /* sentinel */ }
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};
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static const struct ddrphy_init_sequence dram_init_sequence[] = {
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{
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"DRAM Initialization",
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MPHY_PIR_DRAMRST | MPHY_PIR_DRAMINIT,
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MPHY_PGSR0_DIDONE,
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0,
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},
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{ /* sentinel */ }
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};
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static const struct ddrphy_init_sequence training_sequence[] = {
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{
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"Write Leveling",
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MPHY_PIR_WL,
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MPHY_PGSR0_WLDONE,
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MPHY_PGSR0_WLERR,
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},
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{
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"Read DQS Gate Training",
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MPHY_PIR_QSGATE,
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MPHY_PGSR0_QSGDONE,
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MPHY_PGSR0_QSGERR,
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},
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{
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"Write Leveling Adjustment",
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MPHY_PIR_WLADJ,
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MPHY_PGSR0_WLADONE,
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MPHY_PGSR0_WLAERR,
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},
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{
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"Read Bit Deskew",
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MPHY_PIR_RDDSKW,
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MPHY_PGSR0_RDDONE,
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MPHY_PGSR0_RDERR,
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},
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{
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"Write Bit Deskew",
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MPHY_PIR_WRDSKW,
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MPHY_PGSR0_WDDONE,
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MPHY_PGSR0_WDERR,
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},
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{
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"Read Eye Training",
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MPHY_PIR_RDEYE,
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MPHY_PGSR0_REDONE,
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MPHY_PGSR0_REERR,
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},
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{
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"Write Eye Training",
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MPHY_PIR_WREYE,
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MPHY_PGSR0_WEDONE,
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MPHY_PGSR0_WEERR,
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},
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{ /* sentinel */ }
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};
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static int __ddrphy_training(void __iomem *phy_base,
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const struct ddrphy_init_sequence *seq)
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{
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const struct ddrphy_init_sequence *s;
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u32 pgsr0;
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u32 init_flag = MPHY_PIR_INIT;
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u32 done_flag = MPHY_PGSR0_IDONE;
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int timeout = 50000; /* 50 msec is long enough */
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#ifdef DISPLAY_ELAPSED_TIME
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ulong start = get_timer(0);
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#endif
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for (s = seq; s->description; s++) {
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init_flag |= s->init_flag;
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done_flag |= s->done_flag;
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}
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writel(init_flag, phy_base + MPHY_PIR);
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do {
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if (--timeout < 0) {
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pr_err("%s: error: timeout during DDR training\n",
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__func__);
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return -ETIMEDOUT;
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}
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udelay(1);
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pgsr0 = readl(phy_base + MPHY_PGSR0);
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} while ((pgsr0 & done_flag) != done_flag);
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for (s = seq; s->description; s++) {
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if (pgsr0 & s->err_flag) {
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pr_err("%s: error: %s failed\n", __func__,
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s->description);
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return -EIO;
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}
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}
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#ifdef DISPLAY_ELAPSED_TIME
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printf("%s: info: elapsed time %ld msec\n", get_timer(start));
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#endif
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return 0;
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}
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static int ddrphy_impedance_calibration(void __iomem *phy_base)
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{
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int ret;
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u32 tmp;
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ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
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if (ret)
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return ret;
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/*
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* Because of a hardware bug, IDONE flag is set when the first ZQ block
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* is calibrated. The flag does not guarantee the completion for all
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* the ZQ blocks. Wait a little more just in case.
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*/
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udelay(1);
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/* reflect ZQ settings and enable average algorithm*/
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tmp = readl(phy_base + MPHY_ZQCR);
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tmp |= MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
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writel(tmp, phy_base + MPHY_ZQCR);
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tmp &= ~MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
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tmp |= MPHY_ZQCR_AVGEN;
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writel(tmp, phy_base + MPHY_ZQCR);
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return 0;
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}
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static int ddrphy_dram_init(void __iomem *phy_base)
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{
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return __ddrphy_training(phy_base, dram_init_sequence);
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}
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static int ddrphy_training(void __iomem *phy_base)
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{
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return __ddrphy_training(phy_base, training_sequence);
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}
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/* UMC */
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static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
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/*
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* The ch2 is a different generation UMC core.
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* The register spec is different, unfortunately.
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*/
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static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
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static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
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static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
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{0x004A071D, 0x0078071D},
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{0x0055081E, 0x0089081E},
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};
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static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
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/* The ch2 is different for some reason only hardware guys know... */
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static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
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static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
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static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
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{
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u32 val;
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int latency;
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val = readl(dc_base + UMC_RDATACTL_D0);
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latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
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latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
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UMC_RDATACTL_RAD2LTY_SHIFT;
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/*
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* UMC works at the half clock rate of the PHY.
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* The LSB of latency is ignored
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*/
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latency += phy_latency & ~1;
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val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
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if (latency > 0xf) {
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val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
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val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
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} else {
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val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
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}
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writel(val, dc_base + UMC_RDATACTL_D0);
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writel(val, dc_base + UMC_RDATACTL_D1);
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readl(dc_base + UMC_RDATACTL_D1); /* relax */
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}
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/* enable/disable auto refresh */
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void umc_refresh_ctrl(void __iomem *dc_base, int enable)
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{
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u32 tmp;
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tmp = readl(dc_base + UMC_SPCSETB);
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tmp &= ~UMC_SPCSETB_AREFMD_MASK;
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if (enable)
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tmp |= UMC_SPCSETB_AREFMD_ARB;
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else
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tmp |= UMC_SPCSETB_AREFMD_REG;
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writel(tmp, dc_base + UMC_SPCSETB);
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udelay(1);
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}
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static void umc_ud_init(void __iomem *umc_base, int ch)
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{
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writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
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if (ch == 2)
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writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
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}
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static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
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unsigned long size, int width, int ch)
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{
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enum dram_size size_e;
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int latency;
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u32 val;
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switch (size) {
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case 0:
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return 0;
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case SZ_256M:
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size_e = DRAM_SZ_256M;
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break;
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case SZ_512M:
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size_e = DRAM_SZ_512M;
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break;
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default:
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pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
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size, ch);
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return -EINVAL;
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}
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writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
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writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
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dc_base + UMC_CMDCTLB);
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writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);
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writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);
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val = 0x000e000e;
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latency = 12;
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/* ES2 inserted one more FF to the logic. */
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if (uniphier_get_soc_model() >= 2)
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latency += 2;
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if (latency > 0xf) {
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val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
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val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
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} else {
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val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
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}
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writel(val, dc_base + UMC_RDATACTL_D0);
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if (width >= 32)
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writel(val, dc_base + UMC_RDATACTL_D1);
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writel(0x04060A02, dc_base + UMC_WDATACTL_D0);
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if (width >= 32)
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writel(0x04060A02, dc_base + UMC_WDATACTL_D1);
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writel(0x04000000, dc_base + UMC_DATASET);
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writel(0x00400020, dc_base + UMC_DCCGCTL);
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writel(0x00000084, dc_base + UMC_FLOWCTLG);
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writel(0x00000000, dc_base + UMC_ACSSETA);
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writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
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dc_base + UMC_FLOWCTLA);
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writel(0x00004400, dc_base + UMC_FLOWCTLC);
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writel(0x200A0A00, dc_base + UMC_SPCSETB);
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writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
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writel(0x0000000D, dc_base + UMC_RESPCTL);
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if (ch != 2) {
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writel(0x00202000, dc_base + UMC_FLOWCTLB);
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writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);
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writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);
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writel(0x00080700, dc_base + UMC_BSICMAPSET);
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} else {
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writel(0x00200000, dc_base + UMC_FLOWCTLB);
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writel(0x00000000, dc_base + UMC_BSICMAPSET);
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}
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writel(0x00000000, dc_base + UMC_ERRMASKA);
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writel(0x00000000, dc_base + UMC_ERRMASKB);
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|
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return 0;
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}
|
|
|
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static int umc_ch_init(void __iomem *umc_ch_base, enum dram_freq freq,
|
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unsigned long size, unsigned int width, int ch)
|
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{
|
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void __iomem *dc_base = umc_ch_base + 0x00011000;
|
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void __iomem *phy_base = umc_ch_base + 0x00030000;
|
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int ret;
|
|
|
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writel(0x00000002, dc_base + UMC_INITSET);
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while (readl(dc_base + UMC_INITSTAT) & BIT(2))
|
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cpu_relax();
|
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|
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/* deassert PHY reset signals */
|
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writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
|
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dc_base + UMC_DIOCTLA);
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|
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ddrphy_init(phy_base, freq, width, ch);
|
|
|
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ret = ddrphy_impedance_calibration(phy_base);
|
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if (ret)
|
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return ret;
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|
|
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ddrphy_dram_init(phy_base);
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if (ret)
|
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return ret;
|
|
|
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ret = umc_dc_init(dc_base, freq, size, width, ch);
|
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if (ret)
|
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return ret;
|
|
|
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umc_ud_init(umc_ch_base, ch);
|
|
|
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ret = ddrphy_training(phy_base);
|
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if (ret)
|
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return ret;
|
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|
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udelay(1);
|
|
|
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/* match the system latency between UMC and PHY */
|
|
umc_set_system_latency(dc_base,
|
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ddrphy_get_system_latency(phy_base, width));
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|
|
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udelay(1);
|
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|
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/* stop auto refresh before clearing FIFO in PHY */
|
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umc_refresh_ctrl(dc_base, 0);
|
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ddrphy_fifo_reset(phy_base);
|
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umc_refresh_ctrl(dc_base, 1);
|
|
|
|
udelay(10);
|
|
|
|
return 0;
|
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}
|
|
|
|
static void um_init(void __iomem *um_base)
|
|
{
|
|
writel(0x000000ff, um_base + UMC_MBUS0);
|
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writel(0x000000ff, um_base + UMC_MBUS1);
|
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writel(0x000000ff, um_base + UMC_MBUS2);
|
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writel(0x000000ff, um_base + UMC_MBUS3);
|
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}
|
|
|
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int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd)
|
|
{
|
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void __iomem *um_base = (void __iomem *)0x5b600000;
|
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void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
|
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enum dram_freq freq;
|
|
int ch, ret;
|
|
|
|
switch (bd->dram_freq) {
|
|
case 1866:
|
|
freq = DRAM_FREQ_1866M;
|
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break;
|
|
case 2133:
|
|
freq = DRAM_FREQ_2133M;
|
|
break;
|
|
default:
|
|
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (ch = 0; ch < DRAM_CH_NR; ch++) {
|
|
unsigned long size = bd->dram_ch[ch].size;
|
|
unsigned int width = bd->dram_ch[ch].width;
|
|
|
|
if (size) {
|
|
ret = umc_ch_init(umc_ch_base, freq,
|
|
size / (width / 16), width, ch);
|
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if (ret) {
|
|
pr_err("failed to initialize UMC ch%d\n", ch);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
umc_ch_base += 0x00200000;
|
|
}
|
|
|
|
um_init(um_base);
|
|
|
|
return 0;
|
|
}
|