mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
e985eb14ac
This converts the following to Kconfig: CONFIG_CMD_ASKENV CONFIG_CMD_BMP CONFIG_CMD_BOOTD CONFIG_CMD_CACHE CONFIG_CMD_CRC32 CONFIG_CMD_DHCP CONFIG_CMD_ENV CONFIG_CMD_EXPORTENV CONFIG_CMD_EXT2 CONFIG_CMD_EXT4 CONFIG_CMD_FLASH CONFIG_CMD_FS_GENERIC CONFIG_CMD_FUSE CONFIG_CMD_GPIO CONFIG_CMD_GPT CONFIG_CMD_GREPENV CONFIG_CMD_I2C CONFIG_CMD_IMLS CONFIG_CMD_IMPORTENV CONFIG_CMD_LOADB CONFIG_CMD_LOADS CONFIG_CMD_MEMINFO CONFIG_CMD_MII CONFIG_CMD_MTDPARTS CONFIG_CMD_NAND CONFIG_CMD_NAND_TRIMFFS CONFIG_CMD_NFS CONFIG_CMD_PCA953X CONFIG_CMD_PCA953X_INFO CONFIG_CMD_PCI CONFIG_CMD_PING CONFIG_CMD_READ CONFIG_CMD_SF CONFIG_CMD_SPI CONFIG_CMD_SPL CONFIG_CMD_SPL_WRITE_SIZE CONFIG_CMD_TIME CONFIG_CMD_TRACE CONFIG_CMD_UBI CONFIG_CMD_UBIFS CONFIG_CMD_UNZIP CONFIG_FS_EXT4 Signed-off-by: Tom Rini <trini@konsulko.com>
313 lines
9.7 KiB
C
313 lines
9.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor
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* Copyright 2019-2020 NXP
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*/
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#ifndef __LS1046A_COMMON_H
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#define __LS1046A_COMMON_H
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/* SPL build */
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#ifdef CONFIG_SPL_BUILD
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#define SPL_NO_QBMAN
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#define SPL_NO_FMAN
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#define SPL_NO_ENV
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#define SPL_NO_MISC
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#define SPL_NO_QSPI
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#define SPL_NO_USB
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#define SPL_NO_SATA
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#undef CONFIG_DM_I2C
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#endif
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#if defined(CONFIG_SPL_BUILD) && \
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(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
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#define SPL_NO_MMC
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#endif
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#if defined(CONFIG_SPL_BUILD) && \
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!defined(CONFIG_SPL_FSL_LS_PPA)
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#define SPL_NO_IFC
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#endif
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#define CONFIG_REMAKE_ELF
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#include <asm/arch/stream_id_lsch2.h>
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/* Link Definitions */
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#ifdef CONFIG_TFABOOT
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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#else
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#endif
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/* Serial Port */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* SD boot SPL */
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
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#define CONFIG_SPL_STACK 0x10020000
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#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
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#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#ifdef CONFIG_NXP_ESBC
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw u-boot image instead of fit image.
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*/
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#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
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#else
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#define CONFIG_SYS_MONITOR_LEN 0x100000
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#endif /* ifdef CONFIG_NXP_ESBC */
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#endif
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#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
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#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
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#define CONFIG_SPL_MAX_SIZE 0x1f000
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#define CONFIG_SPL_STACK 0x10020000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SYS_MONITOR_LEN 0x100000
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#endif
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/* NAND SPL */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PBL_PAD
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
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#define CONFIG_SPL_STACK 0x1001f000
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* I2C */
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
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#else
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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/* PCIe */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* SATA */
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#ifndef SPL_NO_SATA
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SATA AHCI_BASE_ADDR
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#endif
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/* MMC */
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#ifndef SPL_NO_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#endif
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/* FMan ucode */
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#ifndef SPL_NO_FMAN
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#endif
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#ifdef CONFIG_TFABOOT
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#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
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#else
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#ifdef CONFIG_SD_BOOT
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/*
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* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
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* about 1MB (2048 blocks), Env is stored after the image, and the env size is
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* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
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*/
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
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#elif defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#else
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#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
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#endif
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#endif
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(SCSI, scsi, 0) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif
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#if defined(CONFIG_TARGET_LS1046AFRWY)
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#define LS1046A_BOOT_SRC_AND_HDR\
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"boot_scripts=ls1046afrwy_boot.scr\0" \
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"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
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#elif defined(CONFIG_TARGET_LS1046AQDS)
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#define LS1046A_BOOT_SRC_AND_HDR\
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"boot_scripts=ls1046aqds_boot.scr\0" \
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"boot_script_hdr=hdr_ls1046aqds_bs.out\0"
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#else
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#define LS1046A_BOOT_SRC_AND_HDR\
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"boot_scripts=ls1046ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1046ardb_bs.out\0"
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#endif
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#ifndef SPL_NO_MISC
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"bootm_size=0x10000000\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_addr=0x61000000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"ramdisk_addr_r=0xa0000000\0" \
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"kernel_start=0x1000000\0" \
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"kernelheader_start=0x600000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernelheader_size=0x40000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"kernelhdr_addr_sd=0x3000\0" \
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"kernelhdr_size_sd=0x10\0" \
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"console=ttyS0,115200\0" \
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CONFIG_MTDPARTS_DEFAULT "\0" \
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BOOTENV \
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LS1046A_BOOT_SRC_AND_HDR \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
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"env exists secureboot " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_start $kernel_size; env exists secureboot " \
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"&& sf read $kernelheader_addr_r $kernelheader_start " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"nand_bootcmd=echo Trying load from nand..;" \
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"nand info; nand read $load_addr " \
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"$kernel_start $kernel_size; env exists secureboot " \
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"&& nand read $kernelheader_addr_r $kernelheader_start " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"nor_bootcmd=echo Trying load from nor..;" \
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"cp.b $kernel_addr $load_addr " \
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"$kernel_size; env exists secureboot " \
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"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"sd_bootcmd=echo Trying load from SD ..;" \
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"mmcinfo; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"env exists secureboot && mmc read $kernelheader_addr_r " \
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$board\0"
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#include <asm/arch/soc.h>
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#endif /* __LS1046A_COMMON_H */
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