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https://github.com/AsahiLinux/u-boot
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3f3255c3d7
This code is part of battery boot support for i.MX28. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/*
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* Freescale i.MX28 Battery measurement init
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include "mx28_init.h"
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void mx28_lradc_init(void)
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{
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struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
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writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr);
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writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr);
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writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr);
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clrsetbits_le32(®s->hw_lradc_ctrl3,
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LRADC_CTRL3_CYCLE_TIME_MASK,
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LRADC_CTRL3_CYCLE_TIME_6MHZ);
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clrsetbits_le32(®s->hw_lradc_ctrl4,
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LRADC_CTRL4_LRADC7SELECT_MASK |
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LRADC_CTRL4_LRADC6SELECT_MASK,
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LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
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LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
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}
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void mx28_lradc_enable_batt_measurement(void)
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{
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struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
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/* Check if the channel is present at all. */
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if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
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return;
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writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr);
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writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr);
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clrsetbits_le32(®s->hw_lradc_conversion,
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LRADC_CONVERSION_SCALE_FACTOR_MASK,
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LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
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writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set);
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/* Configure the channel. */
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writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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®s->hw_lradc_ctrl2_clr);
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writel(0xffffffff, ®s->hw_lradc_ch7_clr);
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clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
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writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr);
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/* Schedule the channel. */
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writel(1 << 7, ®s->hw_lradc_ctrl0_set);
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/* Start the channel sampling. */
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writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
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((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
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100, ®s->hw_lradc_delay3);
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writel(0xffffffff, ®s->hw_lradc_ch7_clr);
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writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set);
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}
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