mirror of
https://github.com/AsahiLinux/u-boot
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8993e54b6f
The following MPC5121e subsystems are supported: - low-level CPU init - NOR Boot Flash (common CFI driver) - DDR SDRAM - FEC - I2C - Watchdog Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Jan Wrobel <wrr@semihalf.com>
126 lines
4.2 KiB
C
126 lines
4.2 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor, Inc.
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* Liberty Eran (liberty@freescale.com)
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*/
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#ifndef __E300_H__
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#define __E300_H__
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#define PVR_E300C1 0x80830000
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#define PVR_E300C2 0x80840000
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#define PVR_E300C3 0x80850000
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#define PVR_E300C4 0x80860000
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/*
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* Hardware Implementation-Dependent Register 0 (HID0)
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*/
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/* #define HID0 1008 already defined in processor.h */
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#define HID0_MASK_MACHINE_CHECK 0x00000000
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#define HID0_ENABLE_MACHINE_CHECK 0x80000000
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#define HID0_DISABLE_CACHE_PARITY 0x00000000
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#define HID0_ENABLE_CACHE_PARITY 0x40000000
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#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
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#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
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#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
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#define HID0_ENABLE_DATE_PARITY 0x10000000
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#define HID0_CORE_CLK_OUT 0x00000000
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#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
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#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
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#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
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#define HID0_DISABLE_DOSE_MODE 0x00000000
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#define HID0_ENABLE_DOSE_MODE 0x00800000
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#define HID0_DISABLE_NAP_MODE 0x00000000
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#define HID0_ENABLE_NAP_MODE 0x00400000
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#define HID0_DISABLE_SLEEP_MODE 0x00000000
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#define HID0_ENABLE_SLEEP_MODE 0x00200000
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#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
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#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
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#define HID0_SOFT_RESET 0x00010000
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#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
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#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
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#define HID0_DISABLE_DATA_CACHE 0x00000000
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#define HID0_ENABLE_DATA_CACHE 0x00004000
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#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
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#define HID0_LOCK_DATA_CACHE 0x00001000
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#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
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#define HID0_INVALIDATE_DATA_CACHE 0x00000400
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#define HID0_DISABLE_M_BIT 0x00000000
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#define HID0_ENABLE_M_BIT 0x00000080
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#define HID0_FBIOB 0x00000010
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#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
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#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
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#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
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#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
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/*
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* Hardware Implementation-Dependent Register 2 (HID2)
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*/
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#define HID2 1011
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#define HID2_LET 0x08000000
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#define HID2_HBE 0x00040000
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#define HID2_IWLCK_000 0x00000000 /* no ways locked */
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#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
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#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
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#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
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#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
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#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
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#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
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/* BAT (block address translation */
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#define BATU_BEPI_MSK 0xfffe0000
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#define BATU_BL_MSK 0x00001ffc
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#define BATU_BL_128K 0x00000000
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#define BATU_BL_256K 0x00000004
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#define BATU_BL_512K 0x0000000c
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#define BATU_BL_1M 0x0000001c
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#define BATU_BL_2M 0x0000003c
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#define BATU_BL_4M 0x0000007c
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#define BATU_BL_8M 0x000000fc
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#define BATU_BL_16M 0x000001fc
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#define BATU_BL_32M 0x000003fc
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#define BATU_BL_64M 0x000007fc
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#define BATU_BL_128M 0x00000ffc
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#define BATU_BL_256M 0x00001ffc
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#define BATU_VS 0x00000002
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#define BATU_VP 0x00000001
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#define BATL_BRPN_MSK 0xfffe0000
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#define BATL_WIMG_MSK 0x00000078
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#define BATL_WRITETHROUGH 0x00000040
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#define BATL_CACHEINHIBIT 0x00000020
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#define BATL_MEMCOHERENCE 0x00000010
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#define BATL_GUARDEDSTORAGE 0x00000008
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#define BATL_PP_MSK 0x00000003
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#define BATL_PP_00 0x00000000 /* No access */
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#define BATL_PP_01 0x00000001 /* Read-only */
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#define BATL_PP_10 0x00000002 /* Read-write */
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#define BATL_PP_11 0x00000003
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#endif /* __E300_H__ */
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