mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
4a84cf06aa
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
105 lines
2.1 KiB
C
105 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/timer.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <dm/uclass.h>
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#include <asm/arch/scu_ast2600.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Memory Control registers */
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#define MCR_BASE 0x1e6e0000
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#define MCR_CONF (MCR_BASE + 0x004)
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/* bit fields of MCR_CONF */
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#define MCR_CONF_ECC_EN BIT(7)
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#define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2)
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#define MCR_CONF_VGA_MEMSZ_SHIFT 2
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#define MCR_CONF_MEMSZ_MASK GENMASK(1, 0)
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#define MCR_CONF_MEMSZ_SHIFT 0
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int dram_init(void)
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{
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int ret;
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struct udevice *dev;
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struct ram_info ram;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("cannot get DRAM driver\n");
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("cannot get DRAM information\n");
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return ret;
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}
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gd->ram_size = ram.size;
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return 0;
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}
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int board_init(void)
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{
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int i = 0, rc;
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struct udevice *dev;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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while (1) {
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rc = uclass_get_device(UCLASS_MISC, i++, &dev);
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if (rc)
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break;
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}
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return 0;
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}
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void board_add_ram_info(int use_default)
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{
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int rc;
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uint32_t conf;
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uint32_t ecc, act_size, vga_rsvd;
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struct udevice *scu_dev;
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struct ast2600_scu *scu;
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rc = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
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if (rc) {
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debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
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return;
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}
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scu = devfdt_get_addr_ptr(scu_dev);
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if (IS_ERR_OR_NULL(scu)) {
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debug("%s: cannot get SCU address pointer\n", __func__);
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return;
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}
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conf = readl(MCR_CONF);
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ecc = conf & MCR_CONF_ECC_EN;
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act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
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vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
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/* no VGA reservation if efuse VGA disable bit is set */
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if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
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vga_rsvd = 0;
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printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
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vga_rsvd, (ecc) ? "on" : "off");
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}
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void enable_caches(void)
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{
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/* get rid of the warning message */
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}
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