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d0e6665a24
Add support code for bluestone board wth APM821XX processor based. This patch includes early board init, misc init, configure EBC, initializes UIC, MAKEALL, board.cfg and MAINTAINERS file. Signed-off-by: Tirumala R Marri <tmarri@apm.com Signed-off-by: Stefan Roese <sr@denx.de>
111 lines
3.2 KiB
C
111 lines
3.2 KiB
C
/*
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* Bluestone board support
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*
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* Copyright (c) 2010, Applied Micro Circuits Corporation
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* Author: Tirumala R Marri <tmarri@apm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/apm821xx.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/ppc4xx-gpio.h>
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int board_early_init_f(void)
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{
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC3ER, 0x00000000); /* disable all */
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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/*
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* Configure PFC (Pin Function Control) registers
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* UART0: 2 pins
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*/
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mtsdr(SDR0_PFC1, 0x0000000);
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: Bluestone Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_AHB;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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return 0;
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}
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