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ae525189f0
The comments on the QSPI pad assignments erronously swapped the qspi1_d0 and qspi1_d1 functionality and could cause confusion. QSPI1_D[0] is in fact muxed on pad U1 (gpmc_a16), and QSPI1_D[1] - on pad P3 (gpmc_a17). Fixing comments. Signed-off-by: Lubomir Popov <l-popov@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
144 lines
5.9 KiB
C
144 lines
5.9 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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* Nishant Kamat <nskamat@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MUX_DATA_DRA7XX_H_
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#define _MUX_DATA_DRA7XX_H_
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#include <asm/arch/mux_dra7xx.h>
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const struct pad_conf_entry core_padconf_array_essential[] = {
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{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
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{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
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{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
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{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
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{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
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{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
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{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
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{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
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#if defined(CONFIG_NOR)
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/* NOR only pin-mux */
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{GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
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{GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
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{GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
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{GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
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{GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
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{GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
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{GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
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{GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
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{GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
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{GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
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{GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
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{GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
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{GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
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{GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
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{GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
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{GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
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{GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
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{GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
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{GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
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{GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
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{GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
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{GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
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{GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
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{GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
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{GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
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{GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
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{GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
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#else
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/* eMMC pinmux */
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{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
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{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
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{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
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{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
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{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
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{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
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{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
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{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
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{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
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{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
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#endif
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#if (CONFIG_CONS_INDEX == 1)
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{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
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{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
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{UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
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{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
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#elif (CONFIG_CONS_INDEX == 3)
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{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
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{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
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#endif
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{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
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{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
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{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
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{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
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{RGMII0_TXC, (M0) },
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{RGMII0_TXCTL, (M0) },
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{RGMII0_TXD3, (M0) },
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{RGMII0_TXD2, (M0) },
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{RGMII0_TXD1, (M0) },
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{RGMII0_TXD0, (M0) },
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{RGMII0_RXC, (IEN | M0) },
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{RGMII0_RXCTL, (IEN | M0) },
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{RGMII0_RXD3, (IEN | M0) },
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{RGMII0_RXD2, (IEN | M0) },
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{RGMII0_RXD1, (IEN | M0) },
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{RGMII0_RXD0, (IEN | M0) },
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{VIN2A_D12, (M3) },
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{VIN2A_D13, (M3) },
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{VIN2A_D14, (M3) },
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{VIN2A_D15, (M3) },
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{VIN2A_D16, (M3) },
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{VIN2A_D17, (M3) },
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{VIN2A_D18, (IEN | M3)},
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{VIN2A_D19, (IEN | M3)},
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{VIN2A_D20, (IEN | M3)},
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{VIN2A_D21, (IEN | M3)},
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{VIN2A_D22, (IEN | M3)},
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{VIN2A_D23, (IEN | M3)},
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#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
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/* NAND / NOR pin-mux */
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{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
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{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
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{GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
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{GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
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{GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
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{GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
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{GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
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{GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
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{GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
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{GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
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{GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
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{GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
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{GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
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{GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
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{GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
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{GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
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{GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
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{GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
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{GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
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{GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
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{GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
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{GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
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/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
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#else
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/* QSPI pin-mux */
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{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
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{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
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{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
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{GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
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{GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
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{GPMC_A18, (M1)}, /* QSPI1_SCLK */
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{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
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{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
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{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
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{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
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#endif /* CONFIG_NAND || CONFIG_NOR */
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{USB2_DRVVBUS, (M0 | IEN | FSC) },
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{SPI1_CS1, (PEN | IDIS | M14) },
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};
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#endif /* _MUX_DATA_DRA7XX_H_ */
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