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https://github.com/AsahiLinux/u-boot
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439 lines
15 KiB
C
439 lines
15 KiB
C
/*
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* (C) Copyright 2003
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* EMK Elektronik GmbH <www.emk-elektronik.de>
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* Reinhard Meyer <r.meyer@emk-elektronik.de>
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*
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* Configuation settings for the TOP860 board.
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*
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* -----------------------------------------------------------------
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* TOP860 is a simple module:
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* 16-bit wide FLASH on CS0 (2MB or more)
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* 32-bit wide DRAM on CS2 (either 4MB or 16MB)
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* FEC with Am79C874 100-Base-T and Fiber Optic
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* Ports available, but we choose SMC1 for Console
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* 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
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* 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
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*
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* This config has been copied from MBX.h / MBX860T.h
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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/*-----------------------------------------------------------------------
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* CPU and BOARD type
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
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#define CONFIG_MPC860T 1 /* even better... an FEC! */
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#define CONFIG_TOP860 1 /* ...on a TOP860 module */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_IDENT_STRING " EMK TOP860"
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/*-----------------------------------------------------------------------
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* CLOCK settings
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*/
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#define CONFIG_SYSCLK 49152000
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#define CFG_XTAL 32768
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#define CONFIG_EBDF 1
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#define CONFIG_COM 3
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#define CONFIG_RTC_MPC8xx
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/*-----------------------------------------------------------------------
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* Physical memory map as defined by EMK
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*/
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#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
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#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */
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#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */
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#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */
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#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */
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/*-----------------------------------------------------------------------
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* derived values
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*/
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#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL)
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#define CFG_CPUCLOCK CONFIG_SYSCLK
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#define CFG_BRGCLOCK CONFIG_SYSCLK
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#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_CFI
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/*-----------------------------------------------------------------------
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* Command interpreter
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*/
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_BAUDRATE 9600
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/*
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* Allow partial commands to be matched to uniqueness.
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*/
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#define CFG_MATCH_PARTIAL_CMD
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/*
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* List of available monitor commands. Use the system default list
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* plus add some of the "non-standard" commands back in.
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* See ./cmd_confdefs.h
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*/
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM | \
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CFG_CMD_REGINFO | \
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CFG_CMD_IMMAP | \
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CFG_CMD_ELF | \
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CFG_CMD_DATE | \
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CFG_CMD_MII | \
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CFG_CMD_BEDBUG \
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)
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#define CONFIG_AUTOSCRIPT 1
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#define CFG_LOADS_BAUD_CHANGE 1
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#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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/*-----------------------------------------------------------------------
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* Memory Test Command
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*/
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*-----------------------------------------------------------------------
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* Environment handler
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* only the first 6k in EEPROM are available for user. Of that we use 256b
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*/
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#define CONFIG_SOFT_I2C
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#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
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#define CFG_ENV_OFFSET 0x1000
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#define CFG_ENV_SIZE 0x0700
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_FACT_OFFSET 0x1800
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#define CFG_FACT_SIZE 0x0800
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#define CFG_I2C_FACT_ADDR 0x57
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_SIZE 0x2000
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#define CFG_I2C_SPEED 100000
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#define CFG_I2C_SLAVE 0xFE
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_MISC_INIT_R
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#if defined (CONFIG_SOFT_I2C)
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#define SDA 0x00010
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#define SCL 0x00020
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#define DIR immr->im_cpm.cp_pbdir
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#define DAT immr->im_cpm.cp_pbdat
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#define PAR immr->im_cpm.cp_pbpar
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#define ODR immr->im_cpm.cp_pbodr
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#define I2C_INIT {PAR&=~(SDA|SCL);ODR&=~(SDA|SCL);DAT|=(SDA|SCL);DIR|=(SDA|SCL);}
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#define I2C_READ ((DAT&SDA)?1:0)
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#define I2C_SDA(x) {if(x)DAT|=SDA;else DAT&=~SDA;}
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#define I2C_SCL(x) {if(x)DAT|=SCL;else DAT&=~SCL;}
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#define I2C_DELAY {udelay(5);}
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#define I2C_ACTIVE {DIR|=SDA;}
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#define I2C_TRISTATE {DIR&=~SDA;}
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#endif
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*-----------------------------------------------------------------------
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* defines we need to get FEC running
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*/
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#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
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#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
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#define FEC_ENET 1 /* eth.c needs it that way... */
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#define CFG_DISCOVER_PHY 1
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#define CONFIG_MII 1
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#define CONFIG_PHY_ADDR 31
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/*-----------------------------------------------------------------------
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* adresses
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*/
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x80000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
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#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
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#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Debug Enable Register
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0 /* used in start.S */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set up PLPRCR (PLL, Low-Power, and Reset Control Register)
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* 12 MF calculated Multiplication factor
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* 4 0 0000
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* 1 SPLSS 0 System PLL lock status sticky
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* 1 TEXPS 1 Timer expired status
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* 1 0 0
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* 1 TMIST 0 Timers interrupt status
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* 1 0 0
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* 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
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* 2 LPM 00 Low-power modes
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* 1 CSR 0 Checkstop reset enable
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* 1 LOLRE 0 Loss-of-lock reset enable
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* 1 FIOPD 0 Force I/O pull down
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* 5 0 00000
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*/
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#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20))
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* set up SYPCR:
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* 16 SWTC 0xffff Software watchdog timer count
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* 8 BMT 0xff Bus monitor timing
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* 1 BME 1 Bus monitor enable
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* 3 0 000
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* 1 SWF 1 Software watchdog freeze
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* 1 SWE 0/1 Software watchdog enable
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* 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
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* 1 SWP 0/1 Software watchdog prescale (1=/2048)
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*/
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#if defined (CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* set up SIUMCR
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* 1 EARB 0 External arbitration
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* 3 EARP 000 External arbitration request priority
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* 4 0 0000
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* 1 DSHW 0 Data show cycles
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* 2 DBGC 00 Debug pin configuration
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* 2 DBPC 00 Debug port pins configuration
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* 1 0 0
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* 1 FRC 0 FRZ pin configuration
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* 1 DLK 0 Debug register lock
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* 1 OPAR 0 Odd parity
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* 1 PNCS 0 Parity enable for non memory controller regions
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* 1 DPC 0 Data parity pins configuration
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* 1 MPRE 0 Multiprocessor reservation enable
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* 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
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* 1 AEME 0 Async external master enable
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* 1 SEME 0 Sync external master enable
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* 1 BSC 0 Byte strobe configuration
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* 1 GB5E 0 GPL_B5 enable
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* 1 B2DD 0 Bank 2 double drive
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* 1 B3DD 0 Bank 3 double drive
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* 4 0 0000
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*/
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#define CFG_SIUMCR (SIUMCR_MLRC11)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* set up SCCR (System Clock and Reset Control Register)
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* 1 0 0
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* 2 COM 11 Clock output module (00=full, 01=half, 11=off)
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* 3 0 000
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* 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
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* 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
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* 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
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* 1 CRQEN 0 CPM request enable
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* 1 PRQEN 0 Power management request enable
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* 2 0 00
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* 2 EBDF xx External bus division factor
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* 2 0 00
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* 2 DFSYNC 00 Division factor for SYNCLK
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* 2 DFBRG 00 Division factor for BRGCLK
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* 3 DFNL 000 Division factor low frequency
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* 3 DFNH 000 Division factor high frequency
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* 5 0 00000
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*/
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#define SCCR_MASK 0
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#if CONFIG_EBDF
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#define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
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#else
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#define CFG_SCCR (SCCR_COM11 | SCCR_TBS)
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#endif
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/*-----------------------------------------------------------------------
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* Chip Select 0 - FLASH
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*-----------------------------------------------------------------------
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* Preliminary Values
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*/
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/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
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#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V )
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/*-----------------------------------------------------------------------
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* misc
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*-----------------------------------------------------------------------
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*
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*/
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/*
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* Set the autoboot delay in seconds. A delay of -1 disables autoboot
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*/
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#define CONFIG_BOOTDELAY 5
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/*
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* Pass the clock frequency to the Linux kernel in units of MHz
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*/
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#define CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_PREBOOT \
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"echo;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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/*
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* BOOTP options
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*/
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#undef CONFIG_BOOTP_MASK
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#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_BOOTFILESIZE \
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)
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/*
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* Set default IP stuff just to get bootstrap entries into the
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* environment so that we can autoscript the full default environment.
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*/
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#define CONFIG_ETHADDR 9a:52:63:15:85:25
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#define CONFIG_SERVERIP 10.0.4.200
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#define CONFIG_IPADDR 10.0.4.111
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/*-----------------------------------------------------------------------
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* Defaults for Autoscript
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*/
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_TFTP_LOADADDR 0x00100000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#endif /* __CONFIG_H */
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