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5f3a562a3b
The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_dev_*_ep to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
273 lines
8.4 KiB
C
273 lines
8.4 KiB
C
/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
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*
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* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
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*
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* Registers remapping:
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* Lukasz Majewski <l.majewski@samsumg.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
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#define __ASM_ARCH_REGS_USB_OTG_HS_H
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/* USB2.0 OTG Controller register */
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struct dwc2_usbotg_phy {
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u32 phypwr;
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u32 phyclk;
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u32 rstcon;
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};
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/* Device Logical IN Endpoint-Specific Registers */
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struct dwc2_dev_in_endp {
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u32 diepctl;
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u8 res1[4];
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u32 diepint;
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u8 res2[4];
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u32 dieptsiz;
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u32 diepdma;
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u8 res3[4];
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u32 diepdmab;
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};
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/* Device Logical OUT Endpoint-Specific Registers */
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struct dwc2_dev_out_endp {
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u32 doepctl;
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u8 res1[4];
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u32 doepint;
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u8 res2[4];
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u32 doeptsiz;
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u32 doepdma;
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u8 res3[4];
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u32 doepdmab;
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};
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struct ep_fifo {
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u32 fifo;
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u8 res[4092];
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};
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/* USB2.0 OTG Controller register */
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struct dwc2_usbotg_reg {
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/* Core Global Registers */
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u32 gotgctl; /* OTG Control & Status */
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u32 gotgint; /* OTG Interrupt */
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u32 gahbcfg; /* Core AHB Configuration */
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u32 gusbcfg; /* Core USB Configuration */
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u32 grstctl; /* Core Reset */
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u32 gintsts; /* Core Interrupt */
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u32 gintmsk; /* Core Interrupt Mask */
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u32 grxstsr; /* Receive Status Debug Read/Status Read */
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u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
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u32 grxfsiz; /* Receive FIFO Size */
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u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
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u8 res1[216];
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u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
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u8 res2[1728];
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/* Device Configuration */
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u32 dcfg; /* Device Configuration Register */
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u32 dctl; /* Device Control */
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u32 dsts; /* Device Status */
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u8 res3[4];
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u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
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u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
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u32 daint; /* Device All Endpoints Interrupt */
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u32 daintmsk; /* Device All Endpoints Interrupt Mask */
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u8 res4[224];
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struct dwc2_dev_in_endp in_endp[16];
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struct dwc2_dev_out_endp out_endp[16];
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u8 res5[768];
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struct ep_fifo ep[16];
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};
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/*===================================================================== */
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/*definitions related to CSR setting */
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/* S3C_UDC_OTG_GOTGCTL */
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#define B_SESSION_VALID (0x1<<19)
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#define A_SESSION_VALID (0x1<<18)
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/* S3C_UDC_OTG_GAHBCFG */
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#define PTXFE_HALF (0<<8)
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#define PTXFE_ZERO (1<<8)
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#define NPTXFE_HALF (0<<7)
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#define NPTXFE_ZERO (1<<7)
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#define MODE_SLAVE (0<<5)
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#define MODE_DMA (1<<5)
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#define BURST_SINGLE (0<<1)
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#define BURST_INCR (1<<1)
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#define BURST_INCR4 (3<<1)
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#define BURST_INCR8 (5<<1)
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#define BURST_INCR16 (7<<1)
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#define GBL_INT_UNMASK (1<<0)
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#define GBL_INT_MASK (0<<0)
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/* S3C_UDC_OTG_GRSTCTL */
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#define AHB_MASTER_IDLE (1u<<31)
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#define CORE_SOFT_RESET (0x1<<0)
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/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
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#define INT_RESUME (1u<<31)
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#define INT_DISCONN (0x1<<29)
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#define INT_CONN_ID_STS_CNG (0x1<<28)
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#define INT_OUT_EP (0x1<<19)
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#define INT_IN_EP (0x1<<18)
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#define INT_ENUMDONE (0x1<<13)
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#define INT_RESET (0x1<<12)
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#define INT_SUSPEND (0x1<<11)
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#define INT_EARLY_SUSPEND (0x1<<10)
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#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
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#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
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#define INT_SOF (0x1<<3)
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#define INT_DEV_MODE (0x0<<0)
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#define INT_HOST_MODE (0x1<<1)
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#define INT_GOUTNakEff (0x01<<7)
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#define INT_GINNakEff (0x01<<6)
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#define FULL_SPEED_CONTROL_PKT_SIZE 8
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#define FULL_SPEED_BULK_PKT_SIZE 64
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#define HIGH_SPEED_CONTROL_PKT_SIZE 64
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#define HIGH_SPEED_BULK_PKT_SIZE 512
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#define RX_FIFO_SIZE (1024*4)
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#define NPTX_FIFO_SIZE (1024*4)
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#define PTX_FIFO_SIZE (1536*1)
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#define DEPCTL_TXFNUM_0 (0x0<<22)
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#define DEPCTL_TXFNUM_1 (0x1<<22)
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#define DEPCTL_TXFNUM_2 (0x2<<22)
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#define DEPCTL_TXFNUM_3 (0x3<<22)
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#define DEPCTL_TXFNUM_4 (0x4<<22)
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/* Enumeration speed */
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#define USB_HIGH_30_60MHZ (0x0<<1)
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#define USB_FULL_30_60MHZ (0x1<<1)
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#define USB_LOW_6MHZ (0x2<<1)
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#define USB_FULL_48MHZ (0x3<<1)
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/* S3C_UDC_OTG_GRXSTSP STATUS */
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#define OUT_PKT_RECEIVED (0x2<<17)
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#define OUT_TRANSFER_COMPLELTED (0x3<<17)
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#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
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#define SETUP_PKT_RECEIVED (0x6<<17)
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#define GLOBAL_OUT_NAK (0x1<<17)
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/* S3C_UDC_OTG_DCTL device control register */
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#define NORMAL_OPERATION (0x1<<0)
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#define SOFT_DISCONNECT (0x1<<1)
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/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
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#define DAINT_OUT_BIT (16)
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#define DAINT_MASK (0xFFFF)
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/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
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control IN/OUT endpoint 0 control register */
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#define DEPCTL_EPENA (0x1<<31)
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#define DEPCTL_EPDIS (0x1<<30)
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#define DEPCTL_SETD1PID (0x1<<29)
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#define DEPCTL_SETD0PID (0x1<<28)
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#define DEPCTL_SNAK (0x1<<27)
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#define DEPCTL_CNAK (0x1<<26)
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#define DEPCTL_STALL (0x1<<21)
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#define DEPCTL_TYPE_BIT (18)
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#define DEPCTL_TYPE_MASK (0x3<<18)
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#define DEPCTL_CTRL_TYPE (0x0<<18)
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#define DEPCTL_ISO_TYPE (0x1<<18)
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#define DEPCTL_BULK_TYPE (0x2<<18)
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#define DEPCTL_INTR_TYPE (0x3<<18)
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#define DEPCTL_USBACTEP (0x1<<15)
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#define DEPCTL_NEXT_EP_BIT (11)
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#define DEPCTL_MPS_BIT (0)
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#define DEPCTL_MPS_MASK (0x7FF)
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#define DEPCTL0_MPS_64 (0x0<<0)
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#define DEPCTL0_MPS_32 (0x1<<0)
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#define DEPCTL0_MPS_16 (0x2<<0)
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#define DEPCTL0_MPS_8 (0x3<<0)
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#define DEPCTL_MPS_BULK_512 (512<<0)
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#define DEPCTL_MPS_INT_MPS_16 (16<<0)
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#define DIEPCTL0_NEXT_EP_BIT (11)
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/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
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common interrupt mask register */
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/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
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#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
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#define INTKNEPMIS (0x1<<5)
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#define INTKN_TXFEMP (0x1<<4)
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#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
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#define AHB_ERROR (0x1<<2)
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#define EPDISBLD (0x1<<1)
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#define TRANSFER_DONE (0x1<<0)
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#define USB_PHY_CTRL_EN0 (0x1 << 0)
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/* OPHYPWR */
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#define PHY_0_SLEEP (0x1 << 5)
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#define OTG_DISABLE_0 (0x1 << 4)
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#define ANALOG_PWRDOWN (0x1 << 3)
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#define FORCE_SUSPEND_0 (0x1 << 0)
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/* URSTCON */
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#define HOST_SW_RST (0x1 << 4)
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#define PHY_SW_RST1 (0x1 << 3)
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#define PHYLNK_SW_RST (0x1 << 2)
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#define LINK_SW_RST (0x1 << 1)
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#define PHY_SW_RST0 (0x1 << 0)
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/* OPHYCLK */
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#define COMMON_ON_N1 (0x1 << 7)
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#define COMMON_ON_N0 (0x1 << 4)
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#define ID_PULLUP0 (0x1 << 2)
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#define CLK_SEL_24MHZ (0x3 << 0)
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#define CLK_SEL_12MHZ (0x2 << 0)
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#define CLK_SEL_48MHZ (0x0 << 0)
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#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
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#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
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#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
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#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
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/* Device Configuration Register DCFG */
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#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
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#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
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#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
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#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
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#define EP_MISS_CNT(x) (x << 18)
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#define DEVICE_ADDRESS(x) (x << 4)
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/* Core Reset Register (GRSTCTL) */
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#define TX_FIFO_FLUSH (0x1 << 5)
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#define RX_FIFO_FLUSH (0x1 << 4)
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#define TX_FIFO_NUMBER(x) (x << 6)
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#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
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/* Masks definitions */
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#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
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| INT_RESET | INT_SUSPEND)
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#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
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#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
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#define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
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| GBL_INT_UNMASK)
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/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
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#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
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/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
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#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
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/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
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#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
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#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
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/* Device ALL Endpoints Interrupt Register (DAINT) */
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#define DAINT_IN_EP_INT(x) (x << 0)
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#define DAINT_OUT_EP_INT(x) (x << 16)
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#endif
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