u-boot/arch/arm/cpu
Mingkai Hu d73718f323 armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-08 17:16:49 -04:00
..
arm11 ARM: cache: implement a default weak flush_cache() function 2015-08-12 20:47:48 -04:00
arm720t ARM: ARM720t: remove empty asm/arch/hardware.h 2015-04-23 08:52:27 -04:00
arm920t arm: Allow skipping of low-level init with I-cache on 2016-06-12 23:49:38 +02:00
arm926ejs Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-06-13 08:50:58 -04:00
arm946es arm: Allow skipping of low-level init with I-cache on 2016-06-12 23:49:38 +02:00
arm1136 common: Pass the boot device into spl_boot_mode() 2016-06-26 20:17:22 +02:00
arm1176 ARM: start.S: fix typo 2016-02-29 14:49:35 -05:00
armv7 common: Pass the boot device into spl_boot_mode() 2016-06-26 20:17:22 +02:00
armv7m stm32: move stm32 specific code to mach-stm32 2016-01-20 10:19:41 -05:00
armv8 armv8: Enable CPUECTLR.SMPEN for coherency 2016-07-08 17:16:49 -04:00
pxa pxa: add support for D- and I- caches 2016-03-27 09:13:00 -04:00
sa1100 arm: Allow skipping of low-level init with I-cache on 2016-06-12 23:49:38 +02:00
Makefile Various Makefiles: Add SPDX-License-Identifier tags 2015-11-10 09:19:52 -05:00
u-boot-spl.lds spl: arm: Make sure to include all of the u_boot_list entries 2016-03-16 15:27:55 -04:00
u-boot.lds ARM: allocate extra space for PSCI stack in secure section during link phase 2016-06-20 22:43:59 +02:00