mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-10-04 13:22:20 +00:00
ada02b8463
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> |
||
---|---|---|
.. | ||
ddr |