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3df619ec2c
Add i2c_clk_enable in the cpu specific code, since previous platform it, while new platform don't need. In the pantheon and armada100 platform, this function is defined as NULL one. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
83 lines
3 KiB
C
83 lines
3 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Inc, <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _MV_I2C_H_
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#define _MV_I2C_H_
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extern void i2c_clk_enable(void);
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/* Shall the current transfer have a start/stop condition? */
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#define I2C_COND_NORMAL 0
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#define I2C_COND_START 1
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#define I2C_COND_STOP 2
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/* Shall the current transfer be ack/nacked or being waited for it? */
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#define I2C_ACKNAK_WAITACK 1
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#define I2C_ACKNAK_SENDACK 2
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#define I2C_ACKNAK_SENDNAK 4
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/* Specify who shall transfer the data (master or slave) */
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#define I2C_READ 0
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#define I2C_WRITE 1
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#if (CONFIG_SYS_I2C_SPEED == 400000)
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#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
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| ICR_SCLE)
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#else
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#endif
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#define I2C_ISR_INIT 0x7FF
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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#define ICR_SADIE 0x2000 /* slave address detected int enable */
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#define ICR_UR 0x4000 /* unit reset */
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#define ICR_FM 0x8000 /* Fast Mode */
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/* ----- Status register bits ----------------------------------------- */
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#define ISR_RWM 0x1 /* read/write mode */
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#define ISR_ACKNAK 0x2 /* ack/nak status */
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#define ISR_UB 0x4 /* unit busy */
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#define ISR_IBB 0x8 /* bus busy */
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#define ISR_SSD 0x10 /* slave stop detected */
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#define ISR_ALD 0x20 /* arbitration loss detected */
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#define ISR_ITE 0x40 /* tx buffer empty */
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#define ISR_IRF 0x80 /* rx buffer full */
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#define ISR_GCAD 0x100 /* general call address detected */
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#define ISR_SAD 0x200 /* slave address detected */
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#define ISR_BED 0x400 /* bus error no ACK/NAK */
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#endif
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