mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 18:10:13 +00:00
019df879a9
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
185 lines
3.8 KiB
ArmAsm
185 lines
3.8 KiB
ArmAsm
/*
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* On-chip UART initializaion for low-level debugging
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/serial_reg.h>
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#include <linux/linkage.h>
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#include <mach/bcu-regs.h>
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#include <mach/sc-regs.h>
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#include <mach/sg-regs.h>
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#if !defined(CONFIG_DEBUG_SEMIHOSTING)
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#include CONFIG_DEBUG_LL_INCLUDE
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#endif
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#define BAUDRATE 115200
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#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
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ENTRY(debug_ll_init)
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ldr r0, =SG_REVISION
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ldr r1, [r0]
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and r1, r1, #SG_REVISION_TYPE_MASK
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mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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#define PH1_SLD3_UART_CLK 36864000
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cmp r1, #0x25
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bne ph1_sld3_end
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sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
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ldr r0, =BCSCR5
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ldr r1, =0x24440000
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str r1, [r0]
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_sld3_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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#define PH1_LD4_UART_CLK 36864000
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cmp r1, #0x26
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bne ph1_ld4_end
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ldr r0, =SG_IECTRL
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
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ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_ld4_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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#define PH1_PRO4_UART_CLK 73728000
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cmp r1, #0x28
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bne ph1_pro4_end
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sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
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ldr r0, =SG_LOADPINCTRL
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mov r1, #1
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str r1, [r0]
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_pro4_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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#define PH1_SLD8_UART_CLK 80000000
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cmp r1, #0x29
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bne ph1_sld8_end
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ldr r0, =SG_IECTRL
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
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ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_sld8_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
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#define PH1_PRO5_UART_CLK 73728000
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cmp r1, #0x2A
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bne ph1_pro5_end
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sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
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sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
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sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
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ldr r0, =SG_LOADPINCTRL
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mov r1, #1
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str r1, [r0]
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_pro5_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
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#define PROXSTREAM2_UART_CLK 88900000
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cmp r1, #0x2E
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bne proxstream2_end
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ldr r0, =SG_IECTRL
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
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sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
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sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
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b init_uart
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proxstream2_end:
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
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#define PH1_LD6B_UART_CLK 88900000
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cmp r1, #0x2F
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bne ph1_ld6b_end
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ldr r0, =SG_IECTRL
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ldr r1, [r0]
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orr r1, r1, #1
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str r1, [r0]
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sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
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sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
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sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_ld6b_end:
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#endif
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init_uart:
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addruart r0, r1, r2
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mov r1, #UART_LCR_WLEN8 << 8
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str r1, [r0, #0x10]
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str r3, [r0, #0x24]
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mov pc, lr
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ENDPROC(debug_ll_init)
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