mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 16:07:30 +00:00
dad17fd510
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
307 lines
8.4 KiB
C
307 lines
8.4 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#ifdef CONFIG_ARM64
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/*
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* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_WXN (1 << 19) /* Write Permision Imply XN */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define PGTABLE_SIZE (0x10000)
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/* 2MB granularity */
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#define MMU_SECTION_SHIFT 21
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#ifndef __ASSEMBLY__
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enum dcache_option {
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DCACHE_OFF = 0x3,
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};
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#define isb() \
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({asm volatile( \
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"isb" : : : "memory"); \
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})
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#define wfi() \
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({asm volatile( \
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"wfi" : : : "memory"); \
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})
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static inline unsigned int current_el(void)
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{
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unsigned int el;
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asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
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return el >> 2;
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}
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static inline unsigned int get_sctlr(void)
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{
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unsigned int el, val;
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el = current_el();
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if (el == 1)
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asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
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else if (el == 2)
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asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
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else
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asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_sctlr(unsigned int val)
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{
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unsigned int el;
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el = current_el();
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if (el == 1)
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asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
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else if (el == 2)
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asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
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else
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asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
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asm volatile("isb");
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}
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void __asm_flush_dcache_all(void);
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void __asm_invalidate_dcache_all(void);
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void __asm_flush_dcache_range(u64 start, u64 end);
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void __asm_invalidate_tlb_all(void);
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void __asm_invalidate_icache_all(void);
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int __asm_flush_l3_cache(void);
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void armv8_switch_to_el2(void);
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void armv8_switch_to_el1(void);
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void gic_init(void);
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void gic_send_sgi(unsigned long sgino);
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void wait_for_wakeup(void);
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void protect_secure_region(void);
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void smp_kick_all_cpus(void);
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void flush_l3_cache(void);
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARM64 */
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#ifdef __KERNEL__
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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#define CPU_ARCH_ARMv4 2
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#define CPU_ARCH_ARMv4T 3
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#define CPU_ARCH_ARMv5 4
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#define CPU_ARCH_ARMv5T 5
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#define CPU_ARCH_ARMv5TE 6
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#define CPU_ARCH_ARMv5TEJ 7
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#define CPU_ARCH_ARMv6 8
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#define CPU_ARCH_ARMv7 9
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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#define PGTABLE_SIZE (4096 * 4)
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch.
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* (for details, see gcc PR 15089)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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/**
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* save_boot_params() - Save boot parameters before starting reset sequence
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*
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* If you provide this function it will be called immediately U-Boot starts,
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* both for SPL and U-Boot proper.
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*
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* All registers are unchanged from U-Boot entry. No registers need be
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* preserved.
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*
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* This is not a normal C function. There is no stack. Return by branching to
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* save_boot_params_ret.
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
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*/
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/**
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* save_boot_params_ret() - Return from save_boot_params()
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*
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* If you provide save_boot_params(), then you should jump back to this
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* function when done. Try to preserve all registers.
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*
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* If your implementation of save_boot_params() is in C then it is acceptable
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* to simply call save_boot_params_ret() at the end of your function. Since
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* there is no link register set up, you cannot just exit the function. U-Boot
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* will return to the (initialised) value of lr, and likely crash/hang.
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*
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* If your implementation of save_boot_params() is in assembler then you
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* should use 'b' or 'bx' to return to save_boot_params_ret.
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*/
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void save_boot_params_ret(void);
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#define isb() __asm__ __volatile__ ("" : : : "memory")
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#ifdef __ARM_ARCH_7A__
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#else
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#define wfi()
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#endif
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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static inline unsigned int get_dacr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_dacr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifdef CONFIG_ARMV7
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/* Short-Descriptor Translation Table Level 1 Bits */
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#define TTB_SECT_NS_MASK (1 << 19)
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#define TTB_SECT_NG_MASK (1 << 17)
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#define TTB_SECT_S_MASK (1 << 16)
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/* Note: TTB AP bits are set elsewhere */
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#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
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#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
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#define TTB_SECT_XN_MASK (1 << 4)
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#define TTB_SECT_C_MASK (1 << 3)
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#define TTB_SECT_B_MASK (1 << 2)
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#define TTB_SECT (2 << 0)
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
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TTB_SECT_XN_MASK | TTB_SECT,
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DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
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DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
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DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
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};
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#else
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = 0x12,
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DCACHE_WRITETHROUGH = 0x1a,
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DCACHE_WRITEBACK = 0x1e,
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DCACHE_WRITEALLOC = 0x16,
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};
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#endif
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/* Size of an MMU section */
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enum {
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MMU_SECTION_SHIFT = 20,
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MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
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};
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#ifdef CONFIG_ARMV7
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/* TTBR0 bits */
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#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
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#define TTBR0_RGN_NC (0 << 3)
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#define TTBR0_RGN_WBWA (1 << 3)
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#define TTBR0_RGN_WT (2 << 3)
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#define TTBR0_RGN_WB (3 << 3)
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/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
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#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
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#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
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#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
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#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
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#endif
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/**
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* Register an update to the page tables, and flush the TLB
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*
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* \param start start address of update in page table
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* \param stop stop address of update in page table
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*/
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void mmu_page_table_flush(unsigned long start, unsigned long stop);
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#ifdef CONFIG_SYS_NONCACHED_MEMORY
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void noncached_init(void);
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phys_addr_t noncached_alloc(size_t size, size_t align);
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#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif /* CONFIG_ARM64 */
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#ifndef __ASSEMBLY__
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/**
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* Change the cache settings for a region.
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*
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* \param start start address of memory region to change
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* \param size size of memory region to change
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* \param option dcache option to select
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*/
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option);
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#endif /* __ASSEMBLY__ */
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#endif
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