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89f2fa0b5e
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.
Example:
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
};
Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
142 lines
4.5 KiB
C
142 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Rockchip PCIe Headers
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*
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* Copyright (c) 2016 Rockchip, Inc.
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* Copyright (c) 2020 Amarula Solutions(India)
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* Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
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* Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
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*
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*/
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
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#define PCIE_CLIENT_BASE 0x0
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#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
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#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
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#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
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#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
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#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
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#define PCIE_CLIENT_BASIC_STATUS1 0x0048
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#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
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#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
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#define PCIE_LINK_UP(x) \
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(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
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#define PCIE_RC_NORMAL_BASE 0x800000
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#define PCIE_LM_BASE 0x900000
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#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
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#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
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#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
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#define PCIE_LM_RCBARPIE BIT(19)
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#define PCIE_LM_RCBARPIS BIT(20)
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#define PCIE_RC_BASE 0xa00000
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
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#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
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#define PCIE_ATR_BASE 0xc00000
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#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
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#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
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#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
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#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
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#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
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#define PCIE_ATR_HDR_MEM 0x2
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#define PCIE_ATR_HDR_IO 0x6
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#define PCIE_ATR_HDR_CFG_TYPE0 0xa
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#define PCIE_ATR_HDR_CFG_TYPE1 0xb
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#define PCIE_ATR_HDR_RID BIT(23)
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#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
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#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE_MASK(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define PHY_CFG_DATA_SHIFT 7
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#define PHY_CFG_ADDR_SHIFT 1
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#define PHY_CFG_DATA_MASK 0xf
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#define PHY_CFG_ADDR_MASK 0x3f
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#define PHY_CFG_RD_MASK 0x3ff
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#define PHY_CFG_WR_ENABLE 1
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#define PHY_CFG_WR_DISABLE 1
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#define PHY_CFG_WR_SHIFT 0
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#define PHY_CFG_WR_MASK 1
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#define PHY_CFG_PLL_LOCK 0x10
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#define PHY_CFG_CLK_TEST 0x10
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#define PHY_CFG_CLK_SCC 0x12
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#define PHY_CFG_SEPE_RATE BIT(3)
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#define PHY_CFG_PLL_100M BIT(3)
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#define PHY_PLL_LOCKED BIT(9)
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#define PHY_PLL_OUTPUT BIT(10)
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#define PHY_LANE_IDLE_OFF 0x1
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#define PHY_LANE_IDLE_MASK 0x1
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#define PHY_LANE_IDLE_A_SHIFT 3
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#define PHY_LANE_IDLE_B_SHIFT 4
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#define PHY_LANE_IDLE_C_SHIFT 5
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#define PHY_LANE_IDLE_D_SHIFT 6
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#define PCIE_PHY_CONF 0xe220
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#define PCIE_PHY_STATUS 0xe2a4
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#define PCIE_PHY_LANEOFF 0xe214
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struct rockchip_pcie_phy {
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void *reg_base;
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struct clk refclk;
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struct reset_ctl phy_rst;
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struct rockchip_pcie_phy_ops *ops;
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};
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struct rockchip_pcie_phy_ops {
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int (*init)(struct rockchip_pcie_phy *phy);
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int (*exit)(struct rockchip_pcie_phy *phy);
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int (*power_on)(struct rockchip_pcie_phy *phy);
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int (*power_off)(struct rockchip_pcie_phy *phy);
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};
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struct rockchip_pcie {
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fdt_addr_t axi_base;
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fdt_addr_t apb_base;
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int first_busno;
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struct udevice *dev;
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struct rockchip_pcie_phy rk_phy;
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struct rockchip_pcie_phy *phy;
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/* resets */
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struct reset_ctl core_rst;
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struct reset_ctl mgmt_rst;
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struct reset_ctl mgmt_sticky_rst;
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struct reset_ctl pipe_rst;
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struct reset_ctl pm_rst;
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struct reset_ctl pclk_rst;
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struct reset_ctl aclk_rst;
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/* gpio */
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struct gpio_desc ep_gpio;
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/* vpcie regulators */
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struct udevice *vpcie12v;
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struct udevice *vpcie3v3;
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struct udevice *vpcie1v8;
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struct udevice *vpcie0v9;
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};
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int rockchip_pcie_phy_get(struct udevice *dev);
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inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
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{
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return pcie->phy;
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}
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inline
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struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
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{
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return (struct rockchip_pcie_phy_ops *)phy->ops;
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}
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