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https://github.com/AsahiLinux/u-boot
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c12737cea0
Add board specific imx config file with recommended IPU Qos settings and adapted DDR configuration. Signed-off-by: Soeren Moch <smoch@web.de>
115 lines
4 KiB
INI
115 lines
4 KiB
INI
/*
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* Copyright (C) 2017 Soeren Moch <smoch@web.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define __ASSEMBLY__
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#include "asm/arch/crm_regs.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/mx6-ddr.h"
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/* image version 2 for imx6 */
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IMAGE_VERSION 2
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BOOT_FROM sd
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/* set the default clock gates to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
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DATA 4, CCM_CCOSR, 0x000000fb
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
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/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x77177717
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DATA 4, MX6_IOMUXC_GPR7, 0x77177717
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/*
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* DDR3/DDR3L settings
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* use default 40 Ohm pad drive strength, no odt
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* 4x256Mx16 DDR3L-1066 7-7-7
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*/
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/* disable dq pullup */
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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/* disable dqs pullup */
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
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/* set ddr input mode for dq signals */
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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/* set ddr input mode for dqs signals */
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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/* set pad calibration type to DDR3 */
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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/* dqs write delay */
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
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/* dqs read delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/* dqs read gating control */
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
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/* start delay line calibration */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
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/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
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/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
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DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
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/* ODT timing */
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
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/* read odt settings, 120 Ohm */
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
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/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
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/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
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/* 2GiByte RAM at cs0 */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
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/* load mode registers of external ddr chips */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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/* externel chip ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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/* configure and start refreshes, 8 refresh commands at 32 kHz */
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
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/* set automatic self refresh */
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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/* controller configuration finished */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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