mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
203e94f6c9
At present we have three states for the environment, numbered 0, 1 and 2. Add an enum to record this to avoid open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
155 lines
3.5 KiB
C
155 lines
3.5 KiB
C
/* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <console.h>
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#include <environment.h>
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#include <malloc.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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#include "../common/qixis.h"
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#include "t102xqds_qixis.h"
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#include "../common/spl.h"
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L3_SIZE;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, sys_clk, ccb_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
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/*
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* There is T1040 SoC issue where NOR, FPGA are inaccessible during
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* NAND boot because IFC signals > IFC_AD7 are not enabled.
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* This workaround changes RCW source to make all signals enabled.
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*/
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u32 porsr1, pinctl;
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#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
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porsr1 = in_be32(&gur->porsr1);
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pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
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out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
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#endif
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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ccb_clk = sys_clk * plat_ratio / 2;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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ccb_clk / 16 / CONFIG_BAUDRATE);
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#if defined(CONFIG_SPL_MMC_BOOT)
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puts("\nSD boot...\n");
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#elif defined(CONFIG_SPL_SPI_BOOT)
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puts("\nSPI boot...\n");
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#elif defined(CONFIG_SPL_NAND_BOOT)
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puts("\nNAND boot...\n");
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#endif
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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bd_t *bd;
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bd = (bd_t *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
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bd->bi_memsize = CONFIG_SYS_L3_SIZE;
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arch_cpu_init();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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gd->flags |= GD_FLG_FULL_MALLOC_INIT;
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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#endif
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#ifdef CONFIG_SPL_SPI_BOOT
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fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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#endif
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = ENV_VALID;
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i2c_init_all();
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dram_init();
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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fsl_spi_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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