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f4317dbd06
Allwinner H616 supports many types of DRAM. Most notably it supports LPDDR4. However, all commercially available boards at this time use only DDR3, so this commit adds only DDR3 support. Controller and MBUS are very similar to H6 but PHY is completely unknown. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
159 lines
4.5 KiB
C
159 lines
4.5 KiB
C
/*
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* H616 dram controller register and constant defines
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*
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* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* Based on H6 one, which is:
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_SUN50I_H616_H
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#define _SUNXI_DRAM_SUN50I_H616_H
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#include <stdbool.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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enum sunxi_dram_type {
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SUNXI_DRAM_TYPE_DDR3 = 3,
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SUNXI_DRAM_TYPE_DDR4,
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SUNXI_DRAM_TYPE_LPDDR3 = 7,
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SUNXI_DRAM_TYPE_LPDDR4
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};
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/* MBUS part is largely the same as in H6, except for one special register */
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x000 control register */
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u8 reserved_0x004[4]; /* 0x004 */
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u32 unk_0x008; /* 0x008 */
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u32 tmr; /* 0x00c timer register */
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u8 reserved_0x010[4]; /* 0x010 */
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u32 unk_0x014; /* 0x014 */
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u8 reserved_0x018[8]; /* 0x018 */
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u32 maer0; /* 0x020 master enable register 0 */
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u32 maer1; /* 0x024 master enable register 1 */
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u32 maer2; /* 0x028 master enable register 2 */
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u8 reserved_0x02c[468]; /* 0x02c */
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u32 bwcr; /* 0x200 bandwidth control register */
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u8 reserved_0x204[12]; /* 0x204 */
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/*
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* The last master configured by BSP libdram is at 0x49x, so the
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* size of this struct array is set to 41 (0x29) now.
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*/
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struct {
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u32 cfg0; /* 0x0 */
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u32 cfg1; /* 0x4 */
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u8 reserved_0x8[8]; /* 0x8 */
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} master[41]; /* 0x210 + index * 0x10 */
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u8 reserved_0x4a0[96]; /* 0x4a0 */
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u32 unk_0x500; /* 0x500 */
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};
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check_member(sunxi_mctl_com_reg, unk_0x500, 0x500);
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/*
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* Controller registers seems to be the same or at least very similar
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* to those in H6.
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*/
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struct sunxi_mctl_ctl_reg {
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u32 mstr; /* 0x000 */
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u32 statr; /* 0x004 unused */
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u32 mstr1; /* 0x008 unused */
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u32 clken; /* 0x00c */
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u32 mrctrl0; /* 0x010 unused */
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u32 mrctrl1; /* 0x014 unused */
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u32 mrstatr; /* 0x018 unused */
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u32 mrctrl2; /* 0x01c unused */
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u32 derateen; /* 0x020 unused */
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u32 derateint; /* 0x024 unused */
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u8 reserved_0x028[8]; /* 0x028 */
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u32 pwrctl; /* 0x030 unused */
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u32 pwrtmg; /* 0x034 unused */
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u32 hwlpctl; /* 0x038 unused */
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u8 reserved_0x03c[20]; /* 0x03c */
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u32 rfshctl0; /* 0x050 unused */
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u32 rfshctl1; /* 0x054 unused */
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u8 reserved_0x058[8]; /* 0x05c */
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u32 rfshctl3; /* 0x060 */
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u32 rfshtmg; /* 0x064 */
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u8 reserved_0x068[104]; /* 0x068 */
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u32 init[8]; /* 0x0d0 */
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u32 dimmctl; /* 0x0f0 unused */
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u32 rankctl; /* 0x0f4 */
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u8 reserved_0x0f8[8]; /* 0x0f8 */
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u32 dramtmg[17]; /* 0x100 */
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u8 reserved_0x144[60]; /* 0x144 */
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u32 zqctl[3]; /* 0x180 */
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u32 zqstat; /* 0x18c unused */
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u32 dfitmg0; /* 0x190 */
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u32 dfitmg1; /* 0x194 */
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u32 dfilpcfg[2]; /* 0x198 unused */
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u32 dfiupd[3]; /* 0x1a0 */
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u32 reserved_0x1ac; /* 0x1ac */
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u32 dfimisc; /* 0x1b0 */
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u32 dfitmg2; /* 0x1b4 unused */
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u32 dfitmg3; /* 0x1b8 unused */
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u32 dfistat; /* 0x1bc */
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u32 dbictl; /* 0x1c0 */
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u8 reserved_0x1c4[60]; /* 0x1c4 */
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u32 addrmap[12]; /* 0x200 */
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u8 reserved_0x230[16]; /* 0x230 */
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u32 odtcfg; /* 0x240 */
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u32 odtmap; /* 0x244 */
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u8 reserved_0x248[8]; /* 0x248 */
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u32 sched[2]; /* 0x250 */
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u8 reserved_0x258[180]; /* 0x258 */
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u32 dbgcmd; /* 0x30c unused */
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u32 dbgstat; /* 0x310 unused */
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u8 reserved_0x314[12]; /* 0x314 */
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u32 swctl; /* 0x320 */
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u32 swstat; /* 0x324 */
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u8 reserved_0x328[7768];/* 0x328 */
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u32 unk_0x2180; /* 0x2180 */
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u8 reserved_0x2184[188];/* 0x2184 */
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u32 unk_0x2240; /* 0x2240 */
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u8 reserved_0x2244[3900];/* 0x2244 */
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u32 unk_0x3180; /* 0x3180 */
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u8 reserved_0x3184[188];/* 0x3184 */
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u32 unk_0x3240; /* 0x3240 */
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u8 reserved_0x3244[3900];/* 0x3244 */
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u32 unk_0x4180; /* 0x4180 */
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u8 reserved_0x4184[188];/* 0x4184 */
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u32 unk_0x4240; /* 0x4240 */
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};
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check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
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check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
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#define MSTR_DEVICETYPE_DDR3 BIT(0)
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#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
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#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
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#define MSTR_DEVICETYPE_DDR4 BIT(4)
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#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
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#define MSTR_2TMODE BIT(10)
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#define MSTR_BUSWIDTH_FULL (0 << 12)
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#define MSTR_BUSWIDTH_HALF (1 << 12)
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#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
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#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
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struct dram_para {
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u32 clk;
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enum sunxi_dram_type type;
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u8 cols;
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u8 rows;
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u8 ranks;
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u8 bus_full_width;
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};
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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void mctl_set_timing_params(struct dram_para *para);
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#endif /* _SUNXI_DRAM_SUN50I_H616_H */
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