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https://github.com/AsahiLinux/u-boot
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126 lines
3.5 KiB
Text
126 lines
3.5 KiB
Text
Freescale MPC8360EMDS Board
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-----------------------------------------
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1. Board Switches and Jumpers
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1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
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For some reason, the HW designers describe the switch settings
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in terms of 0 and 1, and then map that to physical switches where
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the label "On" refers to logic 0 and "Off" is logic 1.
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Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
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bits may contribute to signals that are numbered based at 0,
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and some of those signals may be high-bit-number-0 too. Heed
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well the names and labels and do not get confused.
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"Off" == 1
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"On" == 0
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SW18 is switch 18 as silk-screened onto the board.
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SW4[8] is the bit labled 8 on Switch 4.
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SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
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SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
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SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
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and bits labeled 8 is set as "Off".
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1.1 For the MPC8360E PB PROTO Board
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First, make sure the board default setting is consistent with the
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document shipped with your board. Then apply the following setting:
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SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
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SW4[1-8]= 0011_0000 (Flash boot on local bus)
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SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
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SW10[1-8]= 0000_1000 (core PLL setting)
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SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
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JP6 1-2
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on board Oscillator: 66M
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2. Memory Map
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2.1. The memory map should look pretty much like this:
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
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0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
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0xc000_0000 0xdfff_ffff Empty 512M
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0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
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0xe020_0000 0xe02f_ffff Empty 1M
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0xe030_0000 0xe03f_ffff PCI IO 1M
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0xe040_0000 0xefff_ffff Empty 252M
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0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
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0xf400_0000 0xf7ff_ffff Empty 64M
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0xf800_0000 0xf800_7fff BCSR on CS1 32K
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0xf800_8000 0xf800_ffff PIB CS4 32K
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0xf801_0000 0xf801_7fff PIB CS5 32K
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0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC8360EMDS.h
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CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360
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CONFIG_MPC8360 MPC8360 specific
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CONFIG_MPC8360EMDS MPC8360EMDS board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC8360EMDS_config
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make
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MPC8360 support PCI in host and slave mode.
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To make u-boot support PCI host 66M :
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1) DIP SW support PCI mode as described in Section 1.1.
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2) Make MPC8360EMDS_HOST_66_config
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To make u-boot support PCI host 33M :
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1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
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2) Make MPC8360EMDS_HOST_33_config
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To make u-boot support PCI slave 66M :
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1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
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2) Make MPC8360EMDS_SLAVE_config
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5. Downloading and Flashing Images
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5.0 Download over serial line using Kermit:
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loadb
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[Drop to kermit:
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^\c
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send <u-boot-bin-image>
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c
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]
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Or via tftp:
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tftp 10000 u-boot.bin
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5.1 Reflash U-boot Image using U-boot
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tftp 20000 u-boot.bin
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protect off fef00000 fef3ffff
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erase fef00000 fef3ffff
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cp.b 20000 fef00000 xxxx
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or
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cp.b 20000 fef00000 3ffff
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You have to supply the correct byte count with 'xxxx' from the TFTP result log.
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Maybe 3ffff will work too, that corresponds to the erased sectors.
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6. Notes
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1) The console baudrate for MPC8360EMDS is 115200bps.
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