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https://github.com/AsahiLinux/u-boot
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8cc92b996d
The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
138 lines
4.3 KiB
C
138 lines
4.3 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dm/device.h>
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#include <dm/pinctrl.h>
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#include "pinctrl-uniphier.h"
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static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
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UNIPHIER_PINCTRL_PIN(32, 8),
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UNIPHIER_PINCTRL_PIN(33, 8),
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UNIPHIER_PINCTRL_PIN(34, 8),
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UNIPHIER_PINCTRL_PIN(35, 8),
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UNIPHIER_PINCTRL_PIN(36, 8),
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UNIPHIER_PINCTRL_PIN(37, 8),
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UNIPHIER_PINCTRL_PIN(38, 8),
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UNIPHIER_PINCTRL_PIN(39, 8),
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UNIPHIER_PINCTRL_PIN(40, 9),
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UNIPHIER_PINCTRL_PIN(41, 0),
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UNIPHIER_PINCTRL_PIN(42, 0),
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UNIPHIER_PINCTRL_PIN(43, 0),
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UNIPHIER_PINCTRL_PIN(44, 0),
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UNIPHIER_PINCTRL_PIN(70, 0),
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UNIPHIER_PINCTRL_PIN(71, 0),
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UNIPHIER_PINCTRL_PIN(102, 10),
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UNIPHIER_PINCTRL_PIN(103, 10),
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UNIPHIER_PINCTRL_PIN(104, 11),
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UNIPHIER_PINCTRL_PIN(105, 11),
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UNIPHIER_PINCTRL_PIN(108, 13),
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UNIPHIER_PINCTRL_PIN(109, 13),
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UNIPHIER_PINCTRL_PIN(112, 0),
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UNIPHIER_PINCTRL_PIN(113, 0),
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UNIPHIER_PINCTRL_PIN(114, 0),
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UNIPHIER_PINCTRL_PIN(115, 0),
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};
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static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
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static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
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static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
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static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
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static const unsigned i2c0_pins[] = {102, 103};
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static const unsigned i2c0_muxvals[] = {0, 0};
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static const unsigned i2c1_pins[] = {104, 105};
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static const unsigned i2c1_muxvals[] = {0, 0};
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static const unsigned i2c2_pins[] = {108, 109};
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static const unsigned i2c2_muxvals[] = {2, 2};
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static const unsigned i2c3_pins[] = {108, 109};
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static const unsigned i2c3_muxvals[] = {3, 3};
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static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
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27, 28, 29, 30, 31};
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static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0};
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static const unsigned nand_cs1_pins[] = {22, 23};
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static const unsigned nand_cs1_muxvals[] = {0, 0};
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static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
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static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
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static const unsigned uart0_pins[] = {70, 71};
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static const unsigned uart0_muxvals[] = {3, 3};
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static const unsigned uart1_pins[] = {114, 115};
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static const unsigned uart1_muxvals[] = {0, 0};
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static const unsigned uart2_pins[] = {112, 113};
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static const unsigned uart2_muxvals[] = {1, 1};
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static const unsigned uart3_pins[] = {110, 111};
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static const unsigned uart3_muxvals[] = {1, 1};
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static const unsigned usb0_pins[] = {41, 42};
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static const unsigned usb0_muxvals[] = {0, 0};
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static const unsigned usb1_pins[] = {43, 44};
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static const unsigned usb1_muxvals[] = {0, 0};
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static const unsigned usb2_pins[] = {114, 115};
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static const unsigned usb2_muxvals[] = {1, 1};
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static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
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UNIPHIER_PINCTRL_GROUP(emmc),
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UNIPHIER_PINCTRL_GROUP(emmc_dat8),
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UNIPHIER_PINCTRL_GROUP(i2c0),
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UNIPHIER_PINCTRL_GROUP(i2c1),
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UNIPHIER_PINCTRL_GROUP(i2c2),
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UNIPHIER_PINCTRL_GROUP(i2c3),
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UNIPHIER_PINCTRL_GROUP(nand),
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UNIPHIER_PINCTRL_GROUP(nand_cs1),
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UNIPHIER_PINCTRL_GROUP(sd),
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UNIPHIER_PINCTRL_GROUP(uart0),
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UNIPHIER_PINCTRL_GROUP(uart1),
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UNIPHIER_PINCTRL_GROUP(uart2),
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UNIPHIER_PINCTRL_GROUP(uart3),
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UNIPHIER_PINCTRL_GROUP(usb0),
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UNIPHIER_PINCTRL_GROUP(usb1),
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UNIPHIER_PINCTRL_GROUP(usb2),
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};
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static const char * const ph1_sld8_functions[] = {
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"emmc",
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"i2c0",
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"i2c1",
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"i2c2",
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"i2c3",
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"nand",
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"sd",
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"uart0",
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"uart1",
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"uart2",
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"uart3",
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"usb0",
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"usb1",
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"usb2",
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};
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static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
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.pins = ph1_sld8_pins,
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.pins_count = ARRAY_SIZE(ph1_sld8_pins),
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.groups = ph1_sld8_groups,
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.groups_count = ARRAY_SIZE(ph1_sld8_groups),
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.functions = ph1_sld8_functions,
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.functions_count = ARRAY_SIZE(ph1_sld8_functions),
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};
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static int ph1_sld8_pinctrl_probe(struct udevice *dev)
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{
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return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata);
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}
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static const struct udevice_id ph1_sld8_pinctrl_match[] = {
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{ .compatible = "socionext,ph1-sld8-pinctrl" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(ph1_sld8_pinctrl) = {
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.name = "ph1-sld8-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = of_match_ptr(ph1_sld8_pinctrl_match),
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.probe = ph1_sld8_pinctrl_probe,
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.remove = uniphier_pinctrl_remove,
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.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
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.ops = &uniphier_pinctrl_ops,
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};
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