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3820020299
Since 0dba45864b ("arm: Init the debug UART") ,
the debug_uart_init is now called from crt.S
It's no longer required to call it from the board file.
With the current code, the banned <debug_uart> is printed twice:
<debug_uart>
<debug_uart>
U-Boot 2022.07-rc4-00089-gee3d158fa8 (Jun 08 2022 - 17:39:29 +0300)
Remove all calls from board_early_init_f .
Suggested-by: Balamanikandan Gunasundar <Balamanikandan.Gunasundar@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
219 lines
5.8 KiB
C
219 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Atmel
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* Bo Shen <voice.shen@atmel.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/sama5d3_smc.h>
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#include <asm/arch/sama5d4.h>
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#include <debug_uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_NAND_ATMEL
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static void sama5d4ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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at91_periph_clk_enable(ATMEL_ID_SMC);
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/* Configure SMC CS3 for NAND */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
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AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
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AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
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at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void sama5d4ek_usb_hw_init(void)
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{
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at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
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at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
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at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_DM_VIDEO
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at91_video_show_board_info();
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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static void sama5d4ek_serial3_hw_init(void)
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{
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at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
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at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_USART3);
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}
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void board_debug_uart_init(void)
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{
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sama5d4ek_serial3_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND_ATMEL
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sama5d4ek_nand_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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sama5d4ek_usb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#if CONFIG_NAND_BOOT
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sama5d4ek_nand_hw_init();
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#endif
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}
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static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddr2->rtr = 0x2b0;
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ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct atmel_mpddrc_config ddr2;
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const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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u32 tmp;
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ddr2_conf(&ddr2);
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/* Enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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at91_system_clk_enable(AT91_PMC_DDR);
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tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
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writel(tmp, &mpddr->rd_data_path);
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tmp = readl(&mpddr->io_calibr);
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tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
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ATMEL_MPDDRC_IO_CALIBR_TZQIO |
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ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
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ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
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ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
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ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
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ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
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writel(tmp, &mpddr->io_calibr);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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void at91_pmc_init(void)
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{
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u32 tmp;
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(87) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
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tmp = AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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