mirror of
https://github.com/AsahiLinux/u-boot
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ac45bb1646
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Acked-by: Scott Wood <scottwood@freescale.com>
372 lines
9.6 KiB
C
372 lines
9.6 KiB
C
/*
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* (C) Copyright 2010-2011
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* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
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* esd electronic system design gmbh <www.esd.eu>
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*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <netdev.h>
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#ifdef CONFIG_LCD
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# include <atmel_lcdc.h>
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# include <lcd.h>
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# ifdef CONFIG_LCD_INFO
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# include <nand.h>
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# include <version.h>
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# endif
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static int hw_rev = -1; /* hardware revision */
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int get_hw_rev(void)
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{
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if (hw_rev >= 0)
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return hw_rev;
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hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
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if (hw_rev == 15)
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hw_rev = 0;
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return hw_rev;
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}
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#ifdef CONFIG_CMD_NAND
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static void otc570_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
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at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(12),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif /* CONFIG_CMD_NAND */
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#ifdef CONFIG_MACB
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static void otc570_macb_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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/* Enable clock */
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writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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at91_macb_hw_init();
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}
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#endif
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/*
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* Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
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* controller debugging
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* The ET1100 is located at physical address 0x70000000
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* Its process memory is located at physical address 0x70001000
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*/
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static void otc570_ethercat_hw_init(void)
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{
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at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
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/* Configure SMC EBI1_CS0 for EtherCAT */
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc1->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
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AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
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&smc1->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
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&smc1->cs[0].cycle);
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/*
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* Configure behavior at external wait signal, byte-select mode, 16 bit
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* data bus width, none data float wait states and TDF optimization
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*/
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
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AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
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AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
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/* Configure RDY/BSY */
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at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
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}
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#ifdef CONFIG_LCD
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/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
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vidinfo_t panel_info = {
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.vl_col = 640,
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.vl_row = 480,
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.vl_clk = 25175000,
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.vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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.vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
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.vl_tft = 1, /* 0 = passive, 1 = TFT */
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.vl_vsync_len = 1, /* Length of vertical sync in NOL */
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.vl_upper_margin = 35, /* Idle lines at the frame start */
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.vl_lower_margin = 5, /* Idle lines at the end of the frame */
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.vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
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.vl_left_margin = 112, /* Idle cycles at the line beginning */
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.vl_right_margin = 1, /* Idle cycles at the end of the line */
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
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}
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static void otc570_lcd_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
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at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
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at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
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at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
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writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
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}
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#ifdef CONFIG_LCD_INFO
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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int i;
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char temp[32];
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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lcd_printf("\n%s\n", U_BOOT_VERSION);
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lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
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lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
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dram_size >> 20,
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nand_size >> 20 );
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lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
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lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
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lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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int checkboard(void)
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{
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char str[32];
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puts("Board : esd ARM9 HMI Panel - OTC570");
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if (getenv_f("serial#", str, sizeof(str)) > 0) {
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puts(", serial# ");
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puts(str);
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}
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printf("\n");
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printf("Hardware-revision: 1.%d\n", get_hw_rev());
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printf("Mach-type : %lu\n", gd->bd->bi_arch_number);
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return 0;
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}
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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char *str;
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char *serial = getenv("serial#");
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if (serial) {
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str = strchr(serial, '_');
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if (str && (strlen(str) >= 4)) {
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serialnr->high = (*(str + 1) << 8) | *(str + 2);
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serialnr->low = simple_strtoul(str + 3, NULL, 16);
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}
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} else {
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serialnr->high = 0;
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serialnr->low = 0;
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}
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}
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#endif
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#ifdef CONFIG_REVISION_TAG
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u32 get_board_rev(void)
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{
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return hw_rev | 0x100;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char str[64];
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
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at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
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writel(1 << ATMEL_ID_USART0, &pmc->pcer);
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/* Set USART_MODE = 1 (RS485) */
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writel(1, 0xFFF8C004);
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printf("USART0: ");
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if (getenv_f("usart0", str, sizeof(str)) == -1) {
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printf("No entry - assuming 1-wire\n");
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/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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} else {
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if (strcmp(str, "1-wire") == 0) {
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printf("%s\n", str);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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} else if (strcmp(str, "rs485") == 0) {
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printf("%s\n", str);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
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} else {
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printf("Wrong entry - assuming 1-wire ");
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printf("(valid values are '1-wire' or 'rs485')\n");
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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}
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}
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#ifdef CONFIG_LCD
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printf("Display memory address: 0x%08lX\n", gd->fb_base);
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#endif
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return 0;
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}
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#endif /* CONFIG_MISC_INIT_R */
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int board_early_init_f(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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/* enable all clocks */
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writel((1 << ATMEL_ID_PIOA) |
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(1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOCDE) |
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(1 << ATMEL_ID_TWI) |
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(1 << ATMEL_ID_SPI0) |
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#ifdef CONFIG_LCD
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(1 << ATMEL_ID_LCDC) |
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#endif
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(1 << ATMEL_ID_UHP),
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&pmc->pcer);
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at91_seriald_hw_init();
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/* arch number of OTC570-Board */
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gd->bd->bi_arch_number = MACH_TYPE_OTC570;
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return 0;
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}
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int board_init(void)
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{
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/* initialize ET1100 Controller */
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otc570_ethercat_hw_init();
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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otc570_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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otc570_macb_hw_init();
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#endif
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#ifdef CONFIG_AT91_CAN
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at91_can_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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#ifdef CONFIG_LCD
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otc570_lcd_hw_init();
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#endif
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return 0;
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}
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