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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
267 lines
6.5 KiB
C
267 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Achim Ehrlich <aehrlich@taskit.de>
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* taskit GmbH <www.taskit.de>
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*
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* (C) Copyright 2012-
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* Markus Hubig <mhubig@imko.de>
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* IMKO GmbH <www.imko.de>
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* (C) Copyright 2014
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* Heiko Schocher <hs@denx.de>
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* DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_serial.h>
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#include <asm/arch/at91_spi.h>
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#include <spi.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <watchdog.h>
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# include <net.h>
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#ifndef CONFIG_DM_ETH
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# include <netdev.h>
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#endif
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#include <g_dnl.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void smartweb_request_gpio(void)
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{
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gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
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gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
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gpio_request(AT91_PIN_PA26, "ena PHY");
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}
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static void smartweb_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
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}
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static void smartweb_macb_hw_init(void)
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{
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
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at91_set_gpio_output(AT91_PIN_PA26, 0);
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/*
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* Disable pull-up on:
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* RXDV (PA17) => PHY normal mode (not Test mode)
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* ERX0 (PA14) => PHY ADDR0
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* ERX1 (PA15) => PHY ADDR1
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* ERX2 (PA25) => PHY ADDR2
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* ERX3 (PA26) => PHY ADDR3
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* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28) |
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pin_to_mask(AT91_PIN_PA29),
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&pioa->pudr);
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at91_phy_reset();
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28) |
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pin_to_mask(AT91_PIN_PA29),
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&pioa->puer);
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/* Initialize EMAC=MACB hardware */
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at91_macb_hw_init();
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}
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#ifdef CONFIG_USB_GADGET_AT91
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#include <linux/usb/at91_udc.h>
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void at91_udp_hw_init(void)
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{
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/* Enable PLLB */
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at91_pllb_clk_enable(get_pllb_init());
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/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
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at91_periph_clk_enable(ATMEL_ID_UDP);
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at91_system_clk_enable(AT91SAM926x_PMC_UDP);
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}
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struct at91_udc_data board_udc_data = {
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.baseaddr = ATMEL_BASE_UDP0,
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};
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#endif
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int board_early_init_f(void)
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{
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/* enable this here, as we have SPL without serial support */
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at91_seriald_hw_init();
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smartweb_request_gpio();
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return 0;
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}
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int board_init(void)
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{
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smartweb_request_gpio();
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/* power LED red */
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at91_set_gpio_output(AT91_PIN_PC6, 0);
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at91_set_gpio_output(AT91_PIN_PC7, 1);
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/* alarm LED off */
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at91_set_gpio_output(AT91_PIN_PC8, 0);
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at91_set_gpio_output(AT91_PIN_PC9, 0);
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/* prog LED red */
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at91_set_gpio_output(AT91_PIN_PC10, 0);
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at91_set_gpio_output(AT91_PIN_PC11, 1);
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#ifdef CONFIG_USB_GADGET_AT91
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at91_udp_hw_init();
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at91_udc_probe(&board_udc_data);
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#endif
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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smartweb_nand_hw_init();
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smartweb_macb_hw_init();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(
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(void *)CFG_SYS_SDRAM_BASE,
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CFG_SYS_SDRAM_SIZE);
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return 0;
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}
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#ifndef CONFIG_DM_ETH
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#ifdef CONFIG_MACB
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int board_eth_init(struct bd_info *bis)
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{
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return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
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}
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#endif /* CONFIG_MACB */
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#endif
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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#include <spi_flash.h>
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void matrix_init(void)
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{
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struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
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| AT91_MATRIX_SLOT_CYCLE_(0x40),
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&mat->scfg[3]);
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}
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void at91_spl_board_init(void)
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{
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smartweb_request_gpio();
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/* power LED orange */
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at91_set_gpio_output(AT91_PIN_PC6, 1);
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at91_set_gpio_output(AT91_PIN_PC7, 1);
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/* alarm LED orange */
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at91_set_gpio_output(AT91_PIN_PC8, 1);
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at91_set_gpio_output(AT91_PIN_PC9, 1);
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/* prog LED red */
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at91_set_gpio_output(AT91_PIN_PC10, 0);
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at91_set_gpio_output(AT91_PIN_PC11, 1);
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smartweb_nand_hw_init();
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at91_set_gpio_input(AT91_PIN_PA28, 1);
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at91_set_gpio_input(AT91_PIN_PA29, 1);
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/* check if both button are pressed */
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if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
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at91_get_gpio_value(AT91_PIN_PA29) == 0) {
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smartweb_nand_hw_init();
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nand_init();
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spl_nand_erase_one(0, 0);
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}
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}
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#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
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| AT91_SDRAMC_CAS_2 \
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| AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
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| AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
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| AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
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| AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
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void mem_init(void)
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{
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struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
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struct sdramc_reg setting;
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setting.cr = SDRAM_BASE_CONF;
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setting.mdr = AT91_SDRAMC_MD_SDRAM;
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setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
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/*
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* I write here directly in this register, because this
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* approach is smaller than calling at91_set_a_periph() in a
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* for loop. This saved me 96 bytes.
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*/
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writel(0xffff0000, &port->pdr);
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writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
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sdramc_initialize(ATMEL_BASE_CS1, &setting);
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}
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#endif
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int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
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{
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g_dnl_set_serialnumber("1");
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return 0;
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}
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