Minghuan Lian 1d0b59a9b0 fsl/pci: Set CFG_READY for PCIe v3.0 and later ... Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>		2015-05-04 09:24:23 -07:00
..
asm	fsl/pci: Set CFG_READY for PCIe v3.0 and later	2015-05-04 09:24:23 -07:00