mirror of
https://github.com/AsahiLinux/u-boot
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ac0d98cd55
This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel. Secondary core power down happens in following steps: Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/*
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* Lowlevel setup for EXYNOS5 based board
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*
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* Copyright (C) 2013 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dmc.h>
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#include <asm/arch/power.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/system.h>
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#include "common_setup.h"
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#include "exynos5_setup.h"
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/* These are the things we can do during low-level init */
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enum {
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DO_WAKEUP = 1 << 0,
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DO_CLOCKS = 1 << 1,
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DO_MEM_RESET = 1 << 2,
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DO_UART = 1 << 3,
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DO_POWER = 1 << 4,
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};
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#ifdef CONFIG_EXYNOS5420
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/*
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* Pointer to this function is stored in iRam which is used
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* for jump and power down of a specific core.
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*/
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static void power_down_core(void)
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{
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uint32_t tmp, core_id, core_config;
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/* Get the unique core id */
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/*
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* Multiprocessor Affinity Register
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* [11:8] Cluster ID
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* [1:0] CPU ID
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*/
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mrc_mpafr(core_id);
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tmp = core_id & 0x3;
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core_id = (core_id >> 6) & ~3;
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core_id |= tmp;
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core_id &= 0x3f;
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/* Set the status of the core to low */
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core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
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core_config += EXYNOS5420_CPU_CONFIG_BASE;
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writel(0x0, core_config);
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/* Core enter WFI */
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wfi();
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}
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/*
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* Configurations for secondary cores are inapt at this stage.
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* Reconfigure secondary cores. Shutdown and change the status
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* of all cores except the primary core.
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*/
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static void secondary_cores_configure(void)
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{
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uint32_t core_id;
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/* Store jump address for power down of secondary cores */
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writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
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/* Need all core power down check */
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dsb();
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sev();
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/*
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* Power down all cores(secondary) while primary core must
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* wait for all cores to go down.
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*/
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for (core_id = 1; core_id != CONFIG_CORE_COUNT; core_id++) {
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while ((readl(EXYNOS5420_CPU_STATUS_BASE
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+ (core_id * CPU_CONFIG_STATUS_OFFSET))
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& 0xff) != 0x0) {
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isb();
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sev();
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}
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isb();
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}
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}
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#endif
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int do_lowlevel_init(void)
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{
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uint32_t reset_status;
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int actions = 0;
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arch_cpu_init();
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#ifdef CONFIG_EXYNOS5420
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/* Reconfigure secondary cores */
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secondary_cores_configure();
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#endif
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reset_status = get_reset_status();
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switch (reset_status) {
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case S5P_CHECK_SLEEP:
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actions = DO_CLOCKS | DO_WAKEUP;
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break;
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case S5P_CHECK_DIDLE:
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case S5P_CHECK_LPA:
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actions = DO_WAKEUP;
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break;
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default:
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/* This is a normal boot (not a wake from sleep) */
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actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
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}
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if (actions & DO_POWER)
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set_ps_hold_ctrl();
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if (actions & DO_CLOCKS) {
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system_clock_init();
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mem_ctrl_init(actions & DO_MEM_RESET);
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tzpc_init();
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}
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return actions & DO_WAKEUP;
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}
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