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https://github.com/AsahiLinux/u-boot
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6706b115a6
This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP is integrated in Freescale T1040 and T1020 SoCs. The L2 switch has 10 Ethernet ports: 2 internal fixed-links (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps. The external ports may be connected to PHYs over QSGMII and SGMII. Commands have also been added to enable/disable a port and to check a port's link speed, duplexity and status. The commands are: ethsw port <port_nr> enable|disable - enable/disable an l2 switch port ethsw port <port_nr> show - show an l2 switch port's configuration port_nr=0..9; use "all" for all ports For more detailse please see doc/README.t1040-l2switch Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
402 lines
8.2 KiB
C
402 lines
8.2 KiB
C
/*
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* vsc9953.h
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*
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* Driver for the Vitesse VSC9953 L2 Switch
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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*/
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#ifndef _VSC9953_H_
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#define _VSC9953_H_
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#include <config.h>
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#include <miiphy.h>
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#include <asm/types.h>
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#include <malloc.h>
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#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
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#define VSC9953_SYS_OFFSET 0x010000
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#define VSC9953_DEV_GMII_OFFSET 0x100000
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#define VSC9953_QSYS_OFFSET 0x200000
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#define VSC9953_ANA_OFFSET 0x280000
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#define VSC9953_DEVCPU_GCB 0x070000
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#define VSC9953_ES0 0x040000
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#define VSC9953_IS1 0x050000
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#define VSC9953_IS2 0x060000
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#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
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#define VSC9953_PHY_REGS_OFFST 0x0000AC
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#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001
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#define CONFIG_VSC9953_CORE_ENABLE 0x80
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#define CONFIG_VSC9953_MEM_ENABLE 0x40
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#define CONFIG_VSC9953_MEM_INIT 0x20
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#define CONFIG_VSC9953_PORT_ENA 0x00003a00
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#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011
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#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011
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#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515
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#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043
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#define CONFIG_VSC9953_CLOCK_CFG 0x00000001
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#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001
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#define CONFIG_VSC9953_PFC_FC 0x00000001
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#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000
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#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000
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#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000
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#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe
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#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
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#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000
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#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee
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#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff
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#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004
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#define VSC9953_MAX_PORTS 10
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#define VSC9953_PORT_CHECK(port) \
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(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
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#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
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( \
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(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
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) ? 0 : 1 \
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)
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#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
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#define MIIMIND_OPR_PEND 0x00000004
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struct vsc9953_mdio_info {
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struct vsc9953_mii_mng *regs;
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char *name;
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};
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/* VSC9953 ANA structure for T1040 U-boot*/
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struct vsc9953_ana_port {
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u32 vlan_cfg;
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u32 drop_cfg;
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u32 qos_cfg;
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u32 vcap_cfg;
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u32 vcap_s1_key_cfg[3];
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u32 vcap_s2_cfg;
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u32 qos_pcp_dei_map_cfg[16];
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u32 cpu_fwd_cfg;
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u32 cpu_fwd_bpdu_cfg;
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u32 cpu_fwd_garp_cfg;
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u32 cpu_fwd_ccm_cfg;
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u32 port_cfg;
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u32 pol_cfg;
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u32 reserved[34];
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};
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struct vsc9953_ana_pol {
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u32 pol_pir_cfg;
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u32 pol_cir_cfg;
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u32 pol_mode_cfg;
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u32 pol_pir_state;
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u32 pol_cir_state;
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u32 reserved1[3];
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};
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struct vsc9953_ana_ana_tables {
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u32 entry_lim[11];
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u32 an_moved;
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u32 mach_data;
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u32 macl_data;
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u32 mac_access;
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u32 mact_indx;
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u32 vlan_access;
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u32 vlan_tidx;
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};
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struct vsc9953_ana_ana {
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u32 adv_learn;
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u32 vlan_mask;
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u32 anag_efil;
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u32 an_events;
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u32 storm_limit_burst;
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u32 storm_limit_cfg[4];
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u32 isolated_prts;
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u32 community_ports;
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u32 auto_age;
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u32 mac_options;
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u32 learn_disc;
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u32 agen_ctrl;
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u32 mirror_ports;
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u32 emirror_ports;
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u32 flooding;
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u32 flooding_ipmc;
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u32 sflow_cfg[11];
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u32 port_mode[12];
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};
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struct vsc9953_ana_pgid {
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u32 port_grp_id[91];
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};
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struct vsc9953_ana_pfc {
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u32 pfc_cfg;
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u32 reserved1[15];
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};
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struct vsc9953_ana_pol_misc {
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u32 pol_flowc[10];
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u32 reserved1[17];
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u32 pol_hyst;
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};
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struct vsc9953_ana_common {
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u32 aggr_cfg;
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u32 cpuq_cfg;
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u32 cpuq_8021_cfg;
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u32 dscp_cfg;
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u32 dscp_rewr_cfg;
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u32 vcap_rng_type_cfg;
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u32 vcap_rng_val_cfg;
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u32 discard_cfg;
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u32 fid_cfg;
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};
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struct vsc9953_analyzer {
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struct vsc9953_ana_port port[11];
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u32 reserved1[9536];
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struct vsc9953_ana_pol pol[164];
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struct vsc9953_ana_ana_tables ana_tables;
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u32 reserved2[14];
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struct vsc9953_ana_ana ana;
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u32 reserved3[22];
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struct vsc9953_ana_pgid port_id_tbl;
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u32 reserved4[549];
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struct vsc9953_ana_pfc pfc[10];
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struct vsc9953_ana_pol_misc pol_misc;
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u32 reserved5[196];
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struct vsc9953_ana_common common;
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};
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/* END VSC9953 ANA structure for T1040 U-boot*/
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/* VSC9953 DEV_GMII structure for T1040 U-boot*/
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struct vsc9953_dev_gmii_port_mode {
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u32 clock_cfg;
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u32 port_misc;
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u32 reserved1;
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u32 eee_cfg;
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};
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struct vsc9953_dev_gmii_mac_cfg_status {
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u32 mac_ena_cfg;
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u32 mac_mode_cfg;
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u32 mac_maxlen_cfg;
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u32 mac_tags_cfg;
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u32 mac_adv_chk_cfg;
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u32 mac_ifg_cfg;
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u32 mac_hdx_cfg;
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u32 mac_fc_mac_low_cfg;
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u32 mac_fc_mac_high_cfg;
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u32 mac_sticky;
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};
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struct vsc9953_dev_gmii {
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struct vsc9953_dev_gmii_port_mode port_mode;
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struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
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};
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/* END VSC9953 DEV_GMII structure for T1040 U-boot*/
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/* VSC9953 QSYS structure for T1040 U-boot*/
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struct vsc9953_qsys_hsch {
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u32 cir_cfg;
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u32 reserved1;
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u32 se_cfg;
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u32 se_dwrr_cfg[8];
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u32 cir_state;
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u32 reserved2[20];
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};
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struct vsc9953_qsys_sys {
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u32 port_mode[12];
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u32 switch_port_mode[11];
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u32 stat_cnt_cfg;
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u32 eee_cfg[10];
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u32 eee_thrs;
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u32 igr_no_sharing;
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u32 egr_no_sharing;
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u32 sw_status[11];
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u32 ext_cpu_cfg;
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u32 cpu_group_map;
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u32 reserved1[23];
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};
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struct vsc9953_qsys_qos_cfg {
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u32 red_profile[16];
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u32 res_qos_mode;
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};
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struct vsc9953_qsys_drop_cfg {
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u32 egr_drop_mode;
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};
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struct vsc9953_qsys_mmgt {
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u32 eq_cntrl;
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u32 reserved1;
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};
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struct vsc9953_qsys_hsch_misc {
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u32 hsch_misc_cfg;
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u32 reserved1[546];
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};
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struct vsc9953_qsys_res_ctrl {
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u32 res_cfg;
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u32 res_stat;
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};
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struct vsc9953_qsys_reg {
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struct vsc9953_qsys_hsch hsch[108];
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struct vsc9953_qsys_sys sys;
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struct vsc9953_qsys_qos_cfg qos_cfg;
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struct vsc9953_qsys_drop_cfg drop_cfg;
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struct vsc9953_qsys_mmgt mmgt;
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struct vsc9953_qsys_hsch_misc hsch_misc;
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struct vsc9953_qsys_res_ctrl res_ctrl[1024];
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};
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/* END VSC9953 QSYS structure for T1040 U-boot*/
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/* VSC9953 SYS structure for T1040 U-boot*/
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struct vsc9953_sys_stat {
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u32 rx_cntrs[64];
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u32 tx_cntrs[64];
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u32 drop_cntrs[64];
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u32 reserved1[6];
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};
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struct vsc9953_sys_sys {
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u32 reset_cfg;
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u32 reserved1;
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u32 vlan_etype_cfg;
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u32 port_mode[12];
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u32 front_port_mode[10];
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u32 frame_aging;
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u32 stat_cfg;
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u32 reserved2[50];
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};
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struct vsc9953_sys_pause_cfg {
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u32 pause_cfg[11];
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u32 pause_tot_cfg;
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u32 tail_drop_level[11];
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u32 tot_tail_drop_lvl;
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u32 mac_fc_cfg[10];
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};
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struct vsc9953_sys_mmgt {
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u16 free_cnt;
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};
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struct vsc9953_system_reg {
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struct vsc9953_sys_stat stat;
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struct vsc9953_sys_sys sys;
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struct vsc9953_sys_pause_cfg pause_cfg;
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struct vsc9953_sys_mmgt mmgt;
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};
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/* END VSC9953 SYS structure for T1040 U-boot*/
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/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
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struct vsc9953_chip_regs {
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u32 chipd_id;
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u32 gpr;
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u32 soft_rst;
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};
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struct vsc9953_gpio {
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u32 gpio_out_set[10];
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u32 gpio_out_clr[10];
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u32 gpio_out[10];
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u32 gpio_in[10];
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};
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struct vsc9953_mii_mng {
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u32 miimstatus;
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u32 reserved1;
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u32 miimcmd;
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u32 miimdata;
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u32 miimcfg;
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u32 miimscan_0;
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u32 miimscan_1;
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u32 miiscan_lst_rslts;
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u32 miiscan_lst_rslts_valid;
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};
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struct vsc9953_mii_read_scan {
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u32 mii_scan_results_sticky[2];
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};
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struct vsc9953_devcpu_gcb {
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struct vsc9953_chip_regs chip_regs;
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struct vsc9953_gpio gpio;
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struct vsc9953_mii_mng mii_mng[2];
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struct vsc9953_mii_read_scan mii_read_scan;
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};
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/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
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/* VSC9953 IS* structure for T1040 U-boot*/
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struct vsc9953_vcap_core_cfg {
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u32 vcap_update_ctrl;
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u32 vcap_mv_cfg;
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};
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struct vsc9953_vcap {
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struct vsc9953_vcap_core_cfg vcap_core_cfg;
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};
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/* END VSC9953 IS* structure for T1040 U-boot*/
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#define VSC9953_PORT_INFO_INITIALIZER(idx) \
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{ \
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.enabled = 0, \
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.phyaddr = 0, \
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.index = idx, \
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.phy_regs = NULL, \
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.enet_if = PHY_INTERFACE_MODE_NONE, \
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.bus = NULL, \
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.phydev = NULL, \
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}
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/* Structure to describe a VSC9953 port */
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struct vsc9953_port_info {
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u8 enabled;
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u8 phyaddr;
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int index;
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void *phy_regs;
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phy_interface_t enet_if;
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struct mii_dev *bus;
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struct phy_device *phydev;
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};
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/* Structure to describe a VSC9953 switch */
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struct vsc9953_info {
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struct vsc9953_port_info port[VSC9953_MAX_PORTS];
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};
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void vsc9953_init(bd_t *bis);
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void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus);
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void vsc9953_port_info_set_phy_address(int port, int address);
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void vsc9953_port_enable(int port);
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void vsc9953_port_disable(int port);
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void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int);
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#endif /* _VSC9953_H_ */
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