u-boot/arch/arm/mach-tegra/tegra20/cpu.c
Simon Glass c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00

60 lines
1.3 KiB
C

// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/pmc.h>
#include <linux/delay.h>
#include "../cpu.h"
static void enable_cpu_power_rail(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);
reg |= CPUPWRREQ_OE;
writel(reg, &pmc->pmc_cntrl);
/*
* The TI PMU65861C needs a 3.75ms delay between enabling
* the power rail and enabling the CPU clock. This delay
* between SM1EN and SM1 is for switching time + the ramp
* up of the voltage to the CPU (VDD_CPU from PMU).
*/
udelay(3750);
}
void start_cpu(u32 reset_vector)
{
/* Enable VDD_CPU */
enable_cpu_power_rail();
/* Hold the CPUs in reset */
reset_A9_cpu(1);
/* Disable the CPU clock */
enable_cpu_clock(0);
/* Enable CoreSight */
clock_enable_coresight(1);
/*
* Set the entry point for CPU execution from reset,
* if it's a non-zero value.
*/
if (reset_vector)
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
/* Enable the CPU clock */
enable_cpu_clock(1);
/* If the CPU doesn't already have power, power it up */
powerup_cpu();
/* Take the CPU out of reset */
reset_A9_cpu(0);
}