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aba27acf67
A set of accessor functions was added to be able to access not only memory mapped FPGA in a generic way. Thanks to Wolfgang Denk for getting this sorted properly. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
122 lines
2.5 KiB
C
122 lines
2.5 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/global_data.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#define REFLECTION_TESTPATTERN 0xdede
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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
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#define REFLECTION_TESTREG reflection_low
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#else
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#define REFLECTION_TESTREG reflection_high
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int get_fpga_state(unsigned dev)
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{
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return gd->arch.fpga_state[dev];
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}
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void print_fpga_state(unsigned dev)
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{
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if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
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puts(" Waiting for FPGA-DONE timed out.\n");
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if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
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puts(" FPGA reflection test failed.\n");
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}
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int board_early_init_f(void)
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{
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unsigned k;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] = 0;
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks
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* -> ca. 15 us
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*/
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mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
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return 0;
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}
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int board_early_init_r(void)
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{
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unsigned k;
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unsigned ctr;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] = 0;
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/*
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* reset FPGA
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*/
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gd405ep_init();
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gd405ep_set_fpga_reset(1);
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gd405ep_setup_hw();
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ctr = 0;
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while (!gd405ep_get_fpga_done(k)) {
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udelay(100000);
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if (ctr++ > 5) {
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gd->arch.fpga_state[k] |=
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FPGA_STATE_DONE_FAILED;
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break;
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}
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}
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}
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udelay(10);
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gd405ep_set_fpga_reset(0);
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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/*
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* wait for fpga out of reset
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*/
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ctr = 0;
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while (1) {
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u16 val;
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FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
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FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
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if (val == REFLECTION_TESTPATTERN_INV)
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break;
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udelay(100000);
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if (ctr++ > 5) {
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gd->arch.fpga_state[k] |=
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FPGA_STATE_REFLECTION_FAILED;
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break;
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}
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}
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}
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return 0;
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}
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