u-boot/arch/arm/dts/cn9131-db-A.dts
Konstantin Porotchkin f29eaadeb5 arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018-2021 Marvell International Ltd.
*/
#include "cn9130-db-A.dts"
#include "cn9131-db.dtsi"
/ {
model = "Marvell CN9131 development board (CP NOR) setup(A)";
compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
&cp1_comphy {
/* Serdes Configuration:
* Lane 0: PCIe0 (x2)
* Lane 1: PCIe0 (x2)
* Lane 2: unconnected
* Lane 3: USB1
* Lane 4: SFP (port 0)
* Lane 5: SATA1
*/
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy3 {
phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "sfi"; /* lane-4 */
marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
};