Peng Fan ab87fc6bbd imx: dma: correct MXS_DMA_ALIGNMENT ... We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>		2015-05-26 14:14:49 +02:00
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asm	imx: dma: correct MXS_DMA_ALIGNMENT	2015-05-26 14:14:49 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00