mirror of
https://github.com/AsahiLinux/u-boot
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93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _PANTHEON_CPU_H
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#define _PANTHEON_CPU_H
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#include <asm/io.h>
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#include <asm/system.h>
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/*
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* Main Power Management (MPMU) Registers
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* Refer Register Datasheet 9.1
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*/
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struct panthmpmu_registers {
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u8 pad0[0x0024];
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u32 ccgr; /*0x0024*/
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u8 pad1[0x0200 - 0x024 - 4];
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u32 wdtpcr; /*0x0200*/
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u8 pad2[0x1020 - 0x200 - 4];
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u32 aprr; /*0x1020*/
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u32 acgr; /*0x1024*/
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};
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/*
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* Application Power Management (APMU) Registers
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* Refer Register Datasheet 9.2
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*/
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struct panthapmu_registers {
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u8 pad0[0x0054];
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u32 sd1; /*0x0054*/
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u8 pad1[0x00e0 - 0x054 - 4];
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u32 sd3; /*0x00e0*/
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};
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/*
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* APB Clock Reset/Control Registers
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* Refer Register Datasheet 6.14
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*/
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struct panthapb_registers {
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u32 uart0; /*0x000*/
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u32 uart1; /*0x004*/
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u32 gpio; /*0x008*/
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u8 pad0[0x02c - 0x08 - 4];
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u32 twsi; /*0x02c*/
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u8 pad1[0x034 - 0x2c - 4];
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u32 timers; /*0x034*/
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};
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/*
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* CPU Interface Registers
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* Refer Register Datasheet 4.3
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*/
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struct panthcpu_registers {
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u32 chip_id; /* Chip Id Reg */
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u32 pad;
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u32 cpu_conf; /* CPU Conf Reg */
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u32 pad1;
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u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
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u32 pad2;
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u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
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u32 mcb_conf; /* MCB Conf Reg */
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u32 sys_boot_ctl; /* Sytem Boot Control */
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};
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/*
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* Functions
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*/
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u32 panth_sdram_base(int);
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u32 panth_sdram_size(int);
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int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
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#endif /* _PANTHEON_CPU_H */
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