mirror of
https://github.com/AsahiLinux/u-boot
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ab80b65957
The early serial should not be configured again in initcode() for BYPASS boot mode and in start() for the other LDR boot modes. In BYPASS boot mode, the start up code is located in Nor flash address other than the DRAM address defined in link script. The code embedded string can't be addressed by its compile time symbol. Calculate it according to the flash offset. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
342 lines
8.7 KiB
C
342 lines
8.7 KiB
C
/*
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* serial.h - common serial defines for early debug and serial driver.
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* any functions defined here must be always_inline since
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* initcode cannot have function calls.
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*
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* Copyright (c) 2004-2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_CPU_SERIAL1_H__
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#define __BFIN_CPU_SERIAL1_H__
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#include <asm/mach-common/bits/uart.h>
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#ifndef __ASSEMBLY__
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#include <asm/clock.h>
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#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
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#ifdef UART_DLL
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# define UART0_DLL UART_DLL
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# if CONFIG_UART_CONSOLE != 0
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# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
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# endif
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#endif
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#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
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#define LOB(x) ((x) & 0xFF)
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#define HIB(x) (((x) >> 8) & 0xFF)
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this.
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*/
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struct bfin_mmr_serial {
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#if BFIN_UART_HW_VER == 2
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u16 dll;
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u16 __pad_0;
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u16 dlh;
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u16 __pad_1;
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u16 gctl;
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u16 __pad_2;
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u16 lcr;
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u16 __pad_3;
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u16 mcr;
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u16 __pad_4;
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u16 lsr;
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u16 __pad_5;
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u16 msr;
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u16 __pad_6;
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u16 scr;
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u16 __pad_7;
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u16 ier_set;
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u16 __pad_8;
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u16 ier_clear;
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u16 __pad_9;
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u16 thr;
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u16 __pad_10;
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u16 rbr;
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u16 __pad_11;
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#else
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union {
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u16 dll;
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u16 thr;
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const u16 rbr;
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};
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const u16 __spad0;
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union {
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u16 dlh;
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u16 ier;
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};
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const u16 __spad1;
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const u16 iir;
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u16 __pad_0;
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u16 lcr;
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u16 __pad_1;
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u16 mcr;
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u16 __pad_2;
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u16 lsr;
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u16 __pad_3;
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u16 msr;
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u16 __pad_4;
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u16 scr;
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u16 __pad_5;
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const u32 __spad2;
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u16 gctl;
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u16 __pad_6;
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#endif
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};
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#define uart_lsr_t uint32_t
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#define _lsr_read(p) bfin_read(&p->lsr)
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#define _lsr_write(p, v) bfin_write(&p->lsr, v)
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#if BFIN_UART_HW_VER == 2
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# define ACCESS_LATCH()
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# define ACCESS_PORT_IER()
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#else
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# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB)
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# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
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#endif
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__attribute__((always_inline))
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static inline void serial_early_do_mach_portmux(char port, int mux_mask,
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int mux_func, int port_pin)
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{
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switch (port) {
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#if defined(__ADSPBF54x__)
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case 'B':
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bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
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~mux_mask) | mux_func);
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bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
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break;
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case 'E':
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bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
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~mux_mask) | mux_func);
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bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
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break;
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#endif
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#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
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case 'F':
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bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
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~mux_mask) | mux_func);
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
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break;
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case 'G':
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bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
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~mux_mask) | mux_func);
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bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
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break;
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case 'H':
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bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
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~mux_mask) | mux_func);
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bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
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break;
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#endif
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default:
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break;
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}
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}
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__attribute__((always_inline))
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static inline void serial_early_do_portmux(void)
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{
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#if defined(__ADSPBF50x__)
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switch (CONFIG_UART_CONSOLE) {
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case 0:
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serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
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PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
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serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
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PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
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break;
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case 1:
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serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
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PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
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serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
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PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
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break;
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}
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#elif defined(__ADSPBF51x__)
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switch (CONFIG_UART_CONSOLE) {
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case 0:
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serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
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PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
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serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
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PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
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break;
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case 1:
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serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
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PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
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serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
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PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
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break;
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}
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#elif defined(__ADSPBF52x__)
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switch (CONFIG_UART_CONSOLE) {
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case 0:
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serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
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PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
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serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
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PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
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break;
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case 1:
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serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
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PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
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serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
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PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
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break;
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}
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#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
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const uint16_t func[] = { PFDE, PFTE, };
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
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(1 << P_IDENT(P_UART(RX))) |
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(1 << P_IDENT(P_UART(TX))));
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#elif defined(__ADSPBF54x__)
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switch (CONFIG_UART_CONSOLE) {
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case 0:
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serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
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PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
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serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
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PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
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break;
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case 1:
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serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
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PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
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serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
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PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
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break;
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case 2:
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serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
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PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
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serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
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PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
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break;
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case 3:
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serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
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PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
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serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
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PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
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break;
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}
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#elif defined(__ADSPBF561__)
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/* UART pins could be GPIO, but they aren't pin muxed. */
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#else
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# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
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# error "missing portmux logic for UART"
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# endif
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#endif
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SSYNC();
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}
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__attribute__((always_inline))
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static inline int uart_init(uint32_t uart_base)
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{
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/* always enable UART -- avoids anomalies 05000309 and 05000350 */
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bfin_write(&pUART->gctl, UCEN);
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/* Set LCR to Word Lengh 8-bit word select */
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bfin_write(&pUART->lcr, WLS_8);
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SSYNC();
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return 0;
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}
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__attribute__((always_inline))
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static inline int serial_early_init(uint32_t uart_base)
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{
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/* handle portmux crap on different Blackfins */
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serial_do_portmux();
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return uart_init(uart_base);
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}
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__attribute__((always_inline))
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static inline int serial_early_uninit(uint32_t uart_base)
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{
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/* disable the UART by clearing UCEN */
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bfin_write(&pUART->gctl, 0);
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return 0;
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}
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__attribute__((always_inline))
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static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
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{
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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/* Program the divisor to get the baud rate we want */
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bfin_write(&pUART->dll, LOB(divisor));
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bfin_write(&pUART->dlh, HIB(divisor));
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SSYNC();
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/* Clear DLAB in LCR to Access THR RBR IER */
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ACCESS_PORT_IER();
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SSYNC();
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}
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__attribute__((always_inline))
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static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
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{
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/* Translate from baud into divisor in terms of SCLK. The
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* weird multiplication is to make sure we over sample just
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* a little rather than under sample the incoming signals.
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*/
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#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
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uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
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- ANOMALY_05000230;
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#else
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uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
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baud * 16) - ANOMALY_05000230;
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#endif
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serial_set_divisor(uart_base, divisor);
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}
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__attribute__((always_inline))
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static inline void serial_early_put_div(uint16_t divisor)
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{
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uint32_t uart_base = UART_BASE;
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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/* Program the divisor to get the baud rate we want */
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bfin_write(&pUART->dll, LOB(divisor));
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bfin_write(&pUART->dlh, HIB(divisor));
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SSYNC();
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/* Clear DLAB in LCR to Access THR RBR IER */
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ACCESS_PORT_IER();
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SSYNC();
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}
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__attribute__((always_inline))
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static inline uint16_t serial_early_get_div(void)
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{
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uint32_t uart_base = UART_BASE;
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/* Set DLAB in LCR to Access DLL and DLH */
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ACCESS_LATCH();
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SSYNC();
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uint8_t dll = bfin_read(&pUART->dll);
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uint8_t dlh = bfin_read(&pUART->dlh);
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uint16_t divisor = (dlh << 8) | dll;
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/* Clear DLAB in LCR to Access THR RBR IER */
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ACCESS_PORT_IER();
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SSYNC();
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return divisor;
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}
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#endif
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#endif
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