mirror of
https://github.com/AsahiLinux/u-boot
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760bce07f1
Fixes this warning: ati_radeon_fb.c: In function 'radeon_probe': ati_radeon_fb.c:598: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'void *' Signed-off-by: Anatolij Gustschin <agust@denx.de>
781 lines
24 KiB
C
781 lines
24 KiB
C
/*
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* ATI Radeon Video card Framebuffer driver.
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Zhang Wei <wei.zhang@freescale.com>
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* Jason Jin <jason.jin@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Some codes of this file is partly ported from Linux kernel
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* ATI video framebuffer driver.
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*
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* Now the driver is tested on below ATI chips:
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* 9200
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* X300
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* X700
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include "videomodes.h"
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#include <radeon.h>
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#include "ati_ids.h"
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#include "ati_radeon_fb.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DPRINT(x...) printf(x)
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#else
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#define DPRINT(x...) do{}while(0)
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#endif
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#ifndef min_t
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#define min_t(type,x,y) \
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({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
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#endif
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#define MAX_MAPPED_VRAM (2048*2048*4)
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#define MIN_MAPPED_VRAM (1024*768*1)
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#define RADEON_BUFFER_ALIGN 0x00000fff
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#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
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& ~RADEON_BUFFER_ALIGN) - 1)
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#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
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((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
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#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
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(((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
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#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
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(((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
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#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
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((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
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#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
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((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
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/*#define PCI_VENDOR_ID_ATI*/
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#define PCI_CHIP_RV280_5960 0x5960
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#define PCI_CHIP_RV280_5961 0x5961
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#define PCI_CHIP_RV280_5962 0x5962
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#define PCI_CHIP_RV280_5964 0x5964
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#define PCI_CHIP_RV280_5C63 0x5C63
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#define PCI_CHIP_RV370_5B60 0x5B60
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#define PCI_CHIP_RV380_5657 0x5657
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#define PCI_CHIP_R420_554d 0x554d
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static struct pci_device_id ati_radeon_pci_ids[] = {
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
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{PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
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{0, 0}
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};
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static u16 ati_radeon_id_family_table[][2] = {
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{PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280},
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{PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
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{PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
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{PCI_CHIP_R420_554d, CHIP_FAMILY_R420},
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{0, 0}
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};
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u16 get_radeon_id_family(u16 device)
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{
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int i;
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for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
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if (ati_radeon_id_family_table[0][i] == device)
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return ati_radeon_id_family_table[0][i + 1];
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return 0;
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}
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struct radeonfb_info *rinfo;
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static void radeon_identify_vram(struct radeonfb_info *rinfo)
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{
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u32 tmp;
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/* framebuffer size */
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if ((rinfo->family == CHIP_FAMILY_RS100) ||
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(rinfo->family == CHIP_FAMILY_RS200) ||
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(rinfo->family == CHIP_FAMILY_RS300)) {
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u32 tom = INREG(NB_TOM);
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tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
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radeon_fifo_wait(6);
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OUTREG(MC_FB_LOCATION, tom);
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OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
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OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
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OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
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/* This is supposed to fix the crtc2 noise problem. */
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OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
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if ((rinfo->family == CHIP_FAMILY_RS100) ||
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(rinfo->family == CHIP_FAMILY_RS200)) {
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/* This is to workaround the asic bug for RMX, some versions
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of BIOS dosen't have this register initialized correctly.
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*/
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OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
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~CRTC_H_CUTOFF_ACTIVE_EN);
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}
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} else {
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tmp = INREG(CONFIG_MEMSIZE);
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}
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/* mem size is bits [28:0], mask off the rest */
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rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
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/*
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* Hack to get around some busted production M6's
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* reporting no ram
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*/
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if (rinfo->video_ram == 0) {
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switch (rinfo->pdev.device) {
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case PCI_CHIP_RADEON_LY:
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case PCI_CHIP_RADEON_LZ:
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rinfo->video_ram = 8192 * 1024;
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break;
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default:
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break;
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}
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}
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/*
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* Now try to identify VRAM type
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*/
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if ((rinfo->family >= CHIP_FAMILY_R300) ||
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(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
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rinfo->vram_ddr = 1;
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else
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rinfo->vram_ddr = 0;
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tmp = INREG(MEM_CNTL);
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if (IS_R300_VARIANT(rinfo)) {
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tmp &= R300_MEM_NUM_CHANNELS_MASK;
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switch (tmp) {
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case 0: rinfo->vram_width = 64; break;
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case 1: rinfo->vram_width = 128; break;
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case 2: rinfo->vram_width = 256; break;
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default: rinfo->vram_width = 128; break;
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}
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} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
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(rinfo->family == CHIP_FAMILY_RS100) ||
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(rinfo->family == CHIP_FAMILY_RS200)){
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if (tmp & RV100_MEM_HALF_MODE)
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rinfo->vram_width = 32;
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else
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rinfo->vram_width = 64;
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} else {
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if (tmp & MEM_NUM_CHANNELS_MASK)
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rinfo->vram_width = 128;
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else
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rinfo->vram_width = 64;
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}
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/* This may not be correct, as some cards can have half of channel disabled
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* ToDo: identify these cases
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*/
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DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n",
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rinfo->video_ram / 1024,
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rinfo->vram_ddr ? "DDR" : "SDRAM",
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rinfo->vram_width);
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}
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static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
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{
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int i;
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radeon_fifo_wait(20);
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#if 0
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/* Workaround from XFree */
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if (rinfo->is_mobility) {
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/* A temporal workaround for the occational blanking on certain laptop
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* panels. This appears to related to the PLL divider registers
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* (fail to lock?). It occurs even when all dividers are the same
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* with their old settings. In this case we really don't need to
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* fiddle with PLL registers. By doing this we can avoid the blanking
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* problem with some panels.
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*/
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if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
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(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
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(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
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/* We still have to force a switch to selected PPLL div thanks to
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* an XFree86 driver bug which will switch it away in some cases
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* even when using UseFDev */
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OUTREGP(CLOCK_CNTL_INDEX,
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mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
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~PPLL_DIV_SEL_MASK);
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radeon_pll_errata_after_index(rinfo);
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radeon_pll_errata_after_data(rinfo);
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return;
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}
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}
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#endif
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if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
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/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
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OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
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/* Reset PPLL & enable atomic update */
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OUTPLLP(PPLL_CNTL,
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PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
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~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
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/* Switch to selected PPLL divider */
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OUTREGP(CLOCK_CNTL_INDEX,
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mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
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~PPLL_DIV_SEL_MASK);
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/* Set PPLL ref. div */
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if (rinfo->family == CHIP_FAMILY_R300 ||
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rinfo->family == CHIP_FAMILY_RS300 ||
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rinfo->family == CHIP_FAMILY_R350 ||
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rinfo->family == CHIP_FAMILY_RV350) {
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if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
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/* When restoring console mode, use saved PPLL_REF_DIV
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* setting.
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*/
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OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
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} else {
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/* R300 uses ref_div_acc field as real ref divider */
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OUTPLLP(PPLL_REF_DIV,
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(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
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~R300_PPLL_REF_DIV_ACC_MASK);
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}
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} else
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OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
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/* Set PPLL divider 3 & post divider*/
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OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
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OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
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/* Write update */
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while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
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;
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OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
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/* Wait read update complete */
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/* FIXME: Certain revisions of R300 can't recover here. Not sure of
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the cause yet, but this workaround will mask the problem for now.
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Other chips usually will pass at the very first test, so the
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workaround shouldn't have any effect on them. */
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for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
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;
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OUTPLL(HTOTAL_CNTL, 0);
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/* Clear reset & atomic update */
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OUTPLLP(PPLL_CNTL, 0,
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~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
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/* We may want some locking ... oh well */
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udelay(5000);
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/* Switch back VCLK source to PPLL */
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OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
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}
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typedef struct {
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u16 reg;
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u32 val;
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} reg_val;
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#if 0 /* unused ? -> scheduled for removal */
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/* these common regs are cleared before mode setting so they do not
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* interfere with anything
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*/
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static reg_val common_regs[] = {
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{ OVR_CLR, 0 },
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{ OVR_WID_LEFT_RIGHT, 0 },
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{ OVR_WID_TOP_BOTTOM, 0 },
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{ OV0_SCALE_CNTL, 0 },
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{ SUBPIC_CNTL, 0 },
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{ VIPH_CONTROL, 0 },
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{ I2C_CNTL_1, 0 },
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{ GEN_INT_CNTL, 0 },
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{ CAP0_TRIG_CNTL, 0 },
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{ CAP1_TRIG_CNTL, 0 },
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};
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#endif /* 0 */
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void radeon_setmode(void)
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{
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struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
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mode->crtc_gen_cntl = 0x03000200;
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mode->crtc_ext_cntl = 0x00008048;
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mode->dac_cntl = 0xff002100;
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mode->crtc_h_total_disp = 0x4f0063;
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mode->crtc_h_sync_strt_wid = 0x8c02a2;
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mode->crtc_v_total_disp = 0x01df020c;
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mode->crtc_v_sync_strt_wid = 0x8201ea;
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mode->crtc_pitch = 0x00500050;
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OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
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OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
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~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
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OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
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OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
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OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
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OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
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OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
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OUTREG(CRTC_OFFSET, 0);
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OUTREG(CRTC_OFFSET_CNTL, 0);
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OUTREG(CRTC_PITCH, mode->crtc_pitch);
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mode->clk_cntl_index = 0x300;
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mode->ppll_ref_div = 0xc;
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mode->ppll_div_3 = 0x00030059;
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radeon_write_pll_regs(rinfo, mode);
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}
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static void set_pal(void)
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{
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int idx, val = 0;
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for (idx = 0; idx < 256; idx++) {
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OUTREG8(PALETTE_INDEX, idx);
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OUTREG(PALETTE_DATA, val);
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val += 0x00010101;
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}
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}
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void radeon_setmode_9200(int vesa_idx, int bpp)
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{
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struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
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mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
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mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
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mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
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mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
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switch (bpp) {
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case 24:
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mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
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#if defined(__BIG_ENDIAN)
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mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
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mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
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#endif
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break;
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case 16:
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mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
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#if defined(__BIG_ENDIAN)
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mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
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mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
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#endif
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break;
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default:
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mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
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mode->surface_cntl = 0x00000000;
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break;
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}
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switch (vesa_idx) {
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case RES_MODE_1280x1024:
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mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
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mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
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mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
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#if defined(CONFIG_RADEON_VREFRESH_75HZ)
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mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
|
|
mode->ppll_div_3 = 0x00010078;
|
|
#else /* default @ 60 Hz */
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
|
|
mode->ppll_div_3 = 0x00010060;
|
|
#endif
|
|
/*
|
|
* for this mode pitch expands to the same value for 32, 16 and 8 bpp,
|
|
* so we set it here once only.
|
|
*/
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
|
|
switch (bpp) {
|
|
case 24:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
|
|
break;
|
|
case 16:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
|
|
break;
|
|
default: /* 8 bpp */
|
|
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
|
|
break;
|
|
}
|
|
break;
|
|
case RES_MODE_1024x768:
|
|
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
|
|
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
|
|
mode->ppll_div_3 = 0x0002008c;
|
|
#else /* @ 60 Hz */
|
|
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
|
|
mode->ppll_div_3 = 0x00020074;
|
|
#endif
|
|
/* also same pitch value for 32, 16 and 8 bpp */
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
|
|
switch (bpp) {
|
|
case 24:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
|
|
break;
|
|
case 16:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
|
|
break;
|
|
default: /* 8 bpp */
|
|
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
|
|
break;
|
|
}
|
|
break;
|
|
case RES_MODE_800x600:
|
|
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
|
|
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
|
|
mode->ppll_div_3 = 0x000300b0;
|
|
#else /* @ 60 Hz */
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
|
|
mode->ppll_div_3 = 0x0003008e;
|
|
#endif
|
|
switch (bpp) {
|
|
case 24:
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
|
|
break;
|
|
case 16:
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
|
|
break;
|
|
default: /* 8 bpp */
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
|
|
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
|
|
break;
|
|
}
|
|
break;
|
|
default: /* RES_MODE_640x480 */
|
|
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
|
|
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
|
|
mode->ppll_div_3 = 0x00030070;
|
|
#else /* @ 60 Hz */
|
|
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
|
|
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
|
|
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
|
|
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
|
|
mode->ppll_div_3 = 0x00030059;
|
|
#endif
|
|
/* also same pitch value for 32, 16 and 8 bpp */
|
|
mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
|
|
switch (bpp) {
|
|
case 24:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
|
|
break;
|
|
case 16:
|
|
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
|
|
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
|
|
break;
|
|
default: /* 8 bpp */
|
|
mode->crtc_offset_cntl = 0x00000000;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
|
|
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
|
|
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
|
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
|
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
|
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
|
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
|
OUTREG(CRTC_OFFSET, 0);
|
|
OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
|
|
OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
|
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
|
|
|
mode->clk_cntl_index = 0x300;
|
|
mode->ppll_ref_div = 0xc;
|
|
|
|
radeon_write_pll_regs(rinfo, mode);
|
|
|
|
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
|
|
OUTREG(SURFACE0_INFO, mode->surf_info[0]);
|
|
OUTREG(SURFACE0_LOWER_BOUND, 0);
|
|
OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
|
|
OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
|
|
|
if (bpp > 8)
|
|
set_pal();
|
|
|
|
free(mode);
|
|
}
|
|
|
|
#include "../bios_emulator/include/biosemu.h"
|
|
extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
|
|
|
|
int radeon_probe(struct radeonfb_info *rinfo)
|
|
{
|
|
pci_dev_t pdev;
|
|
u16 did;
|
|
|
|
pdev = pci_find_devices(ati_radeon_pci_ids, 0);
|
|
|
|
if (pdev != -1) {
|
|
pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
|
|
printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
|
|
PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
|
|
(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
|
|
|
|
strcpy(rinfo->name, "ATI Radeon");
|
|
rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
|
|
rinfo->pdev.device = did;
|
|
rinfo->family = get_radeon_id_family(rinfo->pdev.device);
|
|
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
|
|
&rinfo->fb_base_bus);
|
|
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
|
|
&rinfo->mmio_base_bus);
|
|
rinfo->fb_base_bus &= 0xfffff000;
|
|
rinfo->mmio_base_bus &= ~0x04;
|
|
|
|
rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus,
|
|
PCI_REGION_MEM, 0, MAP_NOCACHE);
|
|
DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n",
|
|
rinfo->mmio_base, rinfo->mmio_base_bus);
|
|
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
|
|
DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
|
|
/* PostBIOS with x86 emulater */
|
|
if (!BootVideoCardBIOS(pdev, NULL, 0))
|
|
return -1;
|
|
|
|
/*
|
|
* Check for errata
|
|
* (These will be added in the future for the chipfamily
|
|
* R300, RV200, RS200, RV100, RS100.)
|
|
*/
|
|
|
|
/* Get VRAM size and type */
|
|
radeon_identify_vram(rinfo);
|
|
|
|
rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
|
|
rinfo->video_ram);
|
|
rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus,
|
|
PCI_REGION_MEM, 0, MAP_NOCACHE);
|
|
DPRINT("Radeon: framebuffer base address 0x%08x, "
|
|
"bus address 0x%08x\n"
|
|
"MMIO base address 0x%08x, bus address 0x%08x, "
|
|
"framebuffer local base 0x%08x.\n ",
|
|
(u32)rinfo->fb_base, rinfo->fb_base_bus,
|
|
(u32)rinfo->mmio_base, rinfo->mmio_base_bus,
|
|
rinfo->fb_local_base);
|
|
return 0;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* The Graphic Device
|
|
*/
|
|
GraphicDevice ctfb;
|
|
|
|
#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
|
|
#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
|
|
#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
|
|
#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
|
|
|
|
void *video_hw_init(void)
|
|
{
|
|
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
|
|
u32 *vm;
|
|
char *penv;
|
|
unsigned long t1, hsynch, vsynch;
|
|
int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
|
|
struct ctfb_res_modes *res_mode;
|
|
struct ctfb_res_modes var_mode;
|
|
|
|
rinfo = malloc(sizeof(struct radeonfb_info));
|
|
|
|
printf("Video: ");
|
|
if(radeon_probe(rinfo)) {
|
|
printf("No radeon video card found!\n");
|
|
return NULL;
|
|
}
|
|
|
|
tmp = 0;
|
|
|
|
videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
|
|
/* get video mode via environment */
|
|
if ((penv = getenv ("videomode")) != NULL) {
|
|
/* deceide if it is a string */
|
|
if (penv[0] <= '9') {
|
|
videomode = (int) simple_strtoul (penv, NULL, 16);
|
|
tmp = 1;
|
|
}
|
|
} else {
|
|
tmp = 1;
|
|
}
|
|
if (tmp) {
|
|
/* parameter are vesa modes */
|
|
/* search params */
|
|
for (i = 0; i < VESA_MODES_COUNT; i++) {
|
|
if (vesa_modes[i].vesanr == videomode)
|
|
break;
|
|
}
|
|
if (i == VESA_MODES_COUNT) {
|
|
printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
|
|
i = 0;
|
|
}
|
|
res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
|
|
bits_per_pixel = vesa_modes[i].bits_per_pixel;
|
|
vesa_idx = vesa_modes[i].resindex;
|
|
} else {
|
|
res_mode = (struct ctfb_res_modes *) &var_mode;
|
|
bits_per_pixel = video_get_params (res_mode, penv);
|
|
}
|
|
|
|
/* calculate hsynch and vsynch freq (info only) */
|
|
t1 = (res_mode->left_margin + res_mode->xres +
|
|
res_mode->right_margin + res_mode->hsync_len) / 8;
|
|
t1 *= 8;
|
|
t1 *= res_mode->pixclock;
|
|
t1 /= 1000;
|
|
hsynch = 1000000000L / t1;
|
|
t1 *= (res_mode->upper_margin + res_mode->yres +
|
|
res_mode->lower_margin + res_mode->vsync_len);
|
|
t1 /= 1000;
|
|
vsynch = 1000000000L / t1;
|
|
|
|
/* fill in Graphic device struct */
|
|
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
|
|
res_mode->yres, bits_per_pixel, (hsynch / 1000),
|
|
(vsynch / 1000));
|
|
printf ("%s\n", pGD->modeIdent);
|
|
pGD->winSizeX = res_mode->xres;
|
|
pGD->winSizeY = res_mode->yres;
|
|
pGD->plnSizeX = res_mode->xres;
|
|
pGD->plnSizeY = res_mode->yres;
|
|
|
|
switch (bits_per_pixel) {
|
|
case 24:
|
|
pGD->gdfBytesPP = 4;
|
|
pGD->gdfIndex = GDF_32BIT_X888RGB;
|
|
if (res_mode->xres == 800) {
|
|
pGD->winSizeX = 832;
|
|
pGD->plnSizeX = 832;
|
|
}
|
|
break;
|
|
case 16:
|
|
pGD->gdfBytesPP = 2;
|
|
pGD->gdfIndex = GDF_16BIT_565RGB;
|
|
if (res_mode->xres == 800) {
|
|
pGD->winSizeX = 896;
|
|
pGD->plnSizeX = 896;
|
|
}
|
|
break;
|
|
default:
|
|
if (res_mode->xres == 800) {
|
|
pGD->winSizeX = 1024;
|
|
pGD->plnSizeX = 1024;
|
|
}
|
|
pGD->gdfBytesPP = 1;
|
|
pGD->gdfIndex = GDF__8BIT_INDEX;
|
|
break;
|
|
}
|
|
|
|
pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
|
|
pGD->pciBase = (unsigned int)rinfo->fb_base;
|
|
pGD->frameAdrs = (unsigned int)rinfo->fb_base;
|
|
pGD->memSize = 64 * 1024 * 1024;
|
|
|
|
/* Cursor Start Address */
|
|
pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) +
|
|
(unsigned int)rinfo->fb_base;
|
|
if ((pGD->dprBase & 0x0fff) != 0) {
|
|
/* allign it */
|
|
pGD->dprBase &= 0xfffff000;
|
|
pGD->dprBase += 0x00001000;
|
|
}
|
|
DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
|
|
PATTERN_ADR);
|
|
pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */
|
|
pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */
|
|
/* set up Hardware */
|
|
|
|
/* Clear video memory (only visible screen area) */
|
|
i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
|
|
vm = (unsigned int *) pGD->pciBase;
|
|
while (i--)
|
|
*vm++ = 0;
|
|
/*SetDrawingEngine (bits_per_pixel);*/
|
|
|
|
if (rinfo->family == CHIP_FAMILY_RV280)
|
|
radeon_setmode_9200(vesa_idx, bits_per_pixel);
|
|
else
|
|
radeon_setmode();
|
|
|
|
return ((void *) pGD);
|
|
}
|
|
|
|
void video_set_lut (unsigned int index, /* color number */
|
|
unsigned char r, /* red */
|
|
unsigned char g, /* green */
|
|
unsigned char b /* blue */
|
|
)
|
|
{
|
|
OUTREG(PALETTE_INDEX, index);
|
|
OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
|
|
}
|