mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 18:10:13 +00:00
160 lines
4 KiB
C
160 lines
4 KiB
C
/*
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* (C) Copyright 2008 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/system.h>
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#ifdef CONFIG_USE_IRQ
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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#ifndef CONFIG_L2_OFF
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void l2cache_disable(void);
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#endif
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static void cache_flush(void);
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int cpu_init(void)
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{
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/*
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* setup up stacks if necessary
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*/
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#ifdef CONFIG_USE_IRQ
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IRQ_STACK_START =
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_armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
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FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
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#endif
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return 0;
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}
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int cleanup_before_linux(void)
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{
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unsigned int i;
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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disable_interrupts();
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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/* invalidate I-cache */
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cache_flush();
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#ifndef CONFIG_L2_OFF
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/* turn off L2 cache */
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l2cache_disable();
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/* invalidate L2 cache also */
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v7_flush_dcache_all(get_device_type());
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#endif
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i = 0;
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/* mem barrier to sync up things */
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asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
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#ifndef CONFIG_L2_OFF
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l2cache_enable();
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#endif
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return 0;
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}
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void l2cache_enable()
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{
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unsigned long i;
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() == CPU_3430_ES2) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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} else {
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/* Save r0, r12 and restore them after usage */
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__asm__ __volatile__("mov %0, r12":"=r"(j));
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__asm__ __volatile__("mov %0, r0":"=r"(i));
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/*
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* GP Device ROM code API usage here
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* r12 = AUXCR Write function and r0 value
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*/
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__asm__ __volatile__("mov r12, #0x3");
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__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
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__asm__ __volatile__("orr r0, r0, #0x2");
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/* SMI instruction to call ROM Code API */
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__asm__ __volatile__(".word 0xE1600070");
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__asm__ __volatile__("mov r0, %0":"=r"(i));
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__asm__ __volatile__("mov r12, %0":"=r"(j));
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}
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}
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void l2cache_disable()
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{
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unsigned long i;
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() == CPU_3430_ES2) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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} else {
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/* Save r0, r12 and restore them after usage */
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__asm__ __volatile__("mov %0, r12":"=r"(j));
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__asm__ __volatile__("mov %0, r0":"=r"(i));
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/*
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* GP Device ROM code API usage here
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* r12 = AUXCR Write function and r0 value
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*/
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__asm__ __volatile__("mov r12, #0x3");
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__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
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__asm__ __volatile__("bic r0, r0, #0x2");
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/* SMI instruction to call ROM Code API */
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__asm__ __volatile__(".word 0xE1600070");
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__asm__ __volatile__("mov r0, %0":"=r"(i));
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__asm__ __volatile__("mov r12, %0":"=r"(j));
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}
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}
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static void cache_flush(void)
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{
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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