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558d06e0a9
spi_init doesn't exist anywhere in the code. Drop it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
412 lines
9.7 KiB
C
412 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Derived from drivers/spi/mpc8xxx_spi.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/soc.h>
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#ifdef CONFIG_ARCH_KIRKWOOD
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#include <asm/arch/mpp.h>
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#endif
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#include <asm/arch-mvebu/spi.h>
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static void _spi_cs_activate(struct kwspi_registers *reg)
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{
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setbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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static void _spi_cs_deactivate(struct kwspi_registers *reg)
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{
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clrbits_le32(®->ctrl, KWSPI_CSN_ACT);
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}
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static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int tmpdout, tmpdin;
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int tm, isread = 0;
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debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
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if (flags & SPI_XFER_BEGIN)
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_spi_cs_activate(reg);
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/*
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* handle data in 8-bit chunks
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* TBD: 2byte xfer mode to be enabled
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*/
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clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
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while (bitlen > 4) {
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debug("loopstart bitlen %d\n", bitlen);
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tmpdout = 0;
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/* Shift data so it's msb-justified */
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if (dout)
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tmpdout = *(u32 *)dout & 0xff;
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clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ);
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writel(tmpdout, ®->dout); /* Write the data out */
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debug("*** spi_xfer: ... %08x written, bitlen %d\n",
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tmpdout, bitlen);
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/*
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* The NE event must be read and cleared first
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*/
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for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
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if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) {
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isread = 1;
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tmpdin = readl(®->din);
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debug("spi_xfer: din %p..%08x read\n",
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din, tmpdin);
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if (din) {
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*((u8 *)din) = (u8)tmpdin;
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din += 1;
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}
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if (dout)
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dout += 1;
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bitlen -= 8;
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}
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if (isread)
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break;
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}
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if (tm >= KWSPI_TIMEOUT)
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printf("*** spi_xfer: Time out during SPI transfer\n");
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debug("loopend bitlen %d\n", bitlen);
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}
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if (flags & SPI_XFER_END)
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_spi_cs_deactivate(reg);
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return 0;
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}
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#ifndef CONFIG_DM_SPI
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static struct kwspi_registers *spireg =
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(struct kwspi_registers *)MVEBU_SPI_BASE;
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#ifdef CONFIG_ARCH_KIRKWOOD
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static u32 cs_spi_mpp_back[2];
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#endif
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct spi_slave *slave;
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u32 data;
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#ifdef CONFIG_ARCH_KIRKWOOD
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static const u32 kwspi_mpp_config[2][2] = {
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{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
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{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
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};
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#endif
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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slave = spi_alloc_slave_base(bus, cs);
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if (!slave)
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return NULL;
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writel(KWSPI_SMEMRDY, &spireg->ctrl);
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/* calculate spi clock prescaller using max_hz */
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data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
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data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
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data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
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/* program spi clock prescaller using max_hz */
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writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
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debug("data = 0x%08x\n", data);
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writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
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writel(KWSPI_IRQMASK, &spireg->irq_mask);
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#ifdef CONFIG_ARCH_KIRKWOOD
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/* program mpp registers to select SPI_CSn */
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kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
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#endif
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return slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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#ifdef CONFIG_ARCH_KIRKWOOD
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kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
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#endif
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free(slave);
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}
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__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return board_spi_claim_bus(slave);
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}
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__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
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{
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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board_spi_release_bus(slave);
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}
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#ifndef CONFIG_SPI_CS_IS_VALID
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/*
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* you can define this function board specific
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* define above CONFIG in board specific config file and
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* provide the function in board specific src file
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*/
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && (cs == 0 || cs == 1);
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}
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#endif
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void spi_cs_activate(struct spi_slave *slave)
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{
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_spi_cs_activate(spireg);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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_spi_cs_deactivate(spireg);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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return _spi_xfer(spireg, bitlen, dout, din, flags);
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}
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#else
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/* Here now the DM part */
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struct mvebu_spi_dev {
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bool is_errata_50mhz_ac;
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};
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struct mvebu_spi_platdata {
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struct kwspi_registers *spireg;
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bool is_errata_50mhz_ac;
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};
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struct mvebu_spi_priv {
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struct kwspi_registers *spireg;
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};
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static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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u32 data;
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/* calculate spi clock prescaller using max_hz */
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data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
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data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
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data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
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/* program spi clock prescaler using max_hz */
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writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
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debug("data = 0x%08x\n", data);
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return 0;
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}
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static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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u32 data;
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/*
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* Erratum description: (Erratum NO. FE-9144572) The device
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* SPI interface supports frequencies of up to 50 MHz.
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* However, due to this erratum, when the device core clock is
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* 250 MHz and the SPI interfaces is configured for 50MHz SPI
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* clock and CPOL=CPHA=1 there might occur data corruption on
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* reads from the SPI device.
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* Erratum Workaround:
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* Work in one of the following configurations:
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* 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
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* Register".
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* 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
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* Register" before setting the interface.
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*/
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data = readl(®->timing1);
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data &= ~KW_SPI_TMISO_SAMPLE_MASK;
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if (CONFIG_SYS_TCLK == 250000000 &&
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mode & SPI_CPOL &&
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mode & SPI_CPHA)
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data |= KW_SPI_TMISO_SAMPLE_2;
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else
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data |= KW_SPI_TMISO_SAMPLE_1;
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writel(data, ®->timing1);
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}
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static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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u32 data = readl(®->cfg);
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data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
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if (mode & SPI_CPHA)
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data |= KWSPI_CPHA;
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if (mode & SPI_CPOL)
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data |= KWSPI_CPOL;
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if (mode & SPI_LSB_FIRST)
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data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
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writel(data, ®->cfg);
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if (plat->is_errata_50mhz_ac)
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mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
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return 0;
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}
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static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
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}
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__attribute__((weak)) int mvebu_board_spi_claim_bus(struct udevice *dev)
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{
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return 0;
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}
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static int mvebu_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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/* Configure the chip-select in the CTRL register */
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clrsetbits_le32(&plat->spireg->ctrl,
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KWSPI_CS_MASK << KWSPI_CS_SHIFT,
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spi_chip_select(dev) << KWSPI_CS_SHIFT);
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return mvebu_board_spi_claim_bus(dev);
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}
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__attribute__((weak)) int mvebu_board_spi_release_bus(struct udevice *dev)
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{
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return 0;
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}
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static int mvebu_spi_release_bus(struct udevice *dev)
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{
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return mvebu_board_spi_release_bus(dev);
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}
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static int mvebu_spi_probe(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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struct kwspi_registers *reg = plat->spireg;
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writel(KWSPI_SMEMRDY, ®->ctrl);
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writel(KWSPI_SMEMRDIRQ, ®->irq_cause);
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writel(KWSPI_IRQMASK, ®->irq_mask);
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return 0;
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}
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static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
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const struct mvebu_spi_dev *drvdata =
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(struct mvebu_spi_dev *)dev_get_driver_data(bus);
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plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
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plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
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return 0;
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}
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static const struct dm_spi_ops mvebu_spi_ops = {
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.claim_bus = mvebu_spi_claim_bus,
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.release_bus = mvebu_spi_release_bus,
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.xfer = mvebu_spi_xfer,
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.set_speed = mvebu_spi_set_speed,
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.set_mode = mvebu_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct mvebu_spi_dev armada_spi_dev_data = {
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.is_errata_50mhz_ac = false,
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};
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static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
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.is_errata_50mhz_ac = false,
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};
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static const struct mvebu_spi_dev armada_375_spi_dev_data = {
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.is_errata_50mhz_ac = false,
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};
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static const struct mvebu_spi_dev armada_380_spi_dev_data = {
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.is_errata_50mhz_ac = true,
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};
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static const struct udevice_id mvebu_spi_ids[] = {
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{
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.compatible = "marvell,orion-spi",
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.data = (ulong)&armada_spi_dev_data,
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},
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{
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.compatible = "marvell,armada-375-spi",
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.data = (ulong)&armada_375_spi_dev_data
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},
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{
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.compatible = "marvell,armada-380-spi",
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.data = (ulong)&armada_380_spi_dev_data
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},
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{
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.compatible = "marvell,armada-xp-spi",
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.data = (ulong)&armada_xp_spi_dev_data
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},
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{ }
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};
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U_BOOT_DRIVER(mvebu_spi) = {
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.name = "mvebu_spi",
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.id = UCLASS_SPI,
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.of_match = mvebu_spi_ids,
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.ops = &mvebu_spi_ops,
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.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
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.probe = mvebu_spi_probe,
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};
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#endif
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