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https://github.com/AsahiLinux/u-boot
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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
142 lines
3.1 KiB
C
142 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/immap.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale MCF5253 DEMO\n");
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return 0;
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};
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int dram_init(void)
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{
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u32 dramsize = 0;
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
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u32 RC, temp;
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RC = (CONFIG_SYS_CLK / 1000000) >> 1;
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RC = (RC * 15) >> 4;
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
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__asm__("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x00003224);
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__asm__("nop");
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/* Initialize DMR0 */
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dramsize = (CFG_SYS_SDRAM_SIZE << 20);
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temp = (dramsize - 1) & 0xFFFC0000;
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mbar_writeLong(MCFSIM_DMR0, temp | 1);
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__asm__("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
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mb();
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__asm__("nop");
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/* Write to this block to initiate precharge */
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*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
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mb();
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__asm__("nop");
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/* Set RE bit in DACR */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x8000);
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__asm__("nop");
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/* Wait for at least 8 auto refresh cycles to occur */
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udelay(500);
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x0040);
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__asm__("nop");
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*(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
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mb();
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}
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gd->ram_size = dramsize;
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return 0;
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}
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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#ifdef CONFIG_IDE
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#include <ata.h>
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void ide_set_reset(int idereset)
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{
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atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
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long period;
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/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
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int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
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{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
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{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
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{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
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{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
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};
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if (idereset) {
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/* control reset */
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out_8(&ata->cr, 0);
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udelay(100);
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} else {
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mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
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#define CALC_TIMING(t) (t + period - 1) / period
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period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
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/*ata->ton = CALC_TIMING (180); */
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out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
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out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
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out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
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out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
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out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
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out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
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out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
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/* IORDY enable */
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out_8(&ata->cr, 0x40);
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udelay(2000);
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/* IORDY enable */
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setbits_8(&ata->cr, 0x01);
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}
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}
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#endif /* CONFIG_IDE */
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(struct bd_info *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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