mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
1fea9e25fa
Add support for enabling and disabling the clock using the clock framework based on the content of OF instead of doing it manually in the board file. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
656 lines
16 KiB
C
656 lines
16 KiB
C
/*
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* drivers/net/ravb.c
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* This file is driver for Renesas Ethernet AVB.
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*
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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*
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* Based on the SuperH Ethernet driver.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <linux/mii.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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/* Registers */
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#define RAVB_REG_CCC 0x000
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#define RAVB_REG_DBAT 0x004
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#define RAVB_REG_CSR 0x00C
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#define RAVB_REG_APSR 0x08C
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#define RAVB_REG_RCR 0x090
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#define RAVB_REG_TGC 0x300
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#define RAVB_REG_TCCR 0x304
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#define RAVB_REG_RIC0 0x360
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#define RAVB_REG_RIC1 0x368
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#define RAVB_REG_RIC2 0x370
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#define RAVB_REG_TIC 0x378
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#define RAVB_REG_ECMR 0x500
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#define RAVB_REG_RFLR 0x508
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#define RAVB_REG_ECSIPR 0x518
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#define RAVB_REG_PIR 0x520
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#define RAVB_REG_GECMR 0x5b0
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#define RAVB_REG_MAHR 0x5c0
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#define RAVB_REG_MALR 0x5c8
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#define CCC_OPC_CONFIG BIT(0)
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#define CCC_OPC_OPERATION BIT(1)
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#define CCC_BOC BIT(20)
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#define CSR_OPS 0x0000000F
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#define CSR_OPS_CONFIG BIT(1)
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#define TCCR_TSRQ0 BIT(0)
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#define RFLR_RFL_MIN 0x05EE
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#define PIR_MDI BIT(3)
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#define PIR_MDO BIT(2)
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#define PIR_MMD BIT(1)
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#define PIR_MDC BIT(0)
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#define ECMR_TRCCM BIT(26)
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#define ECMR_RZPF BIT(20)
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#define ECMR_PFR BIT(18)
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#define ECMR_RXF BIT(17)
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#define ECMR_RE BIT(6)
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#define ECMR_TE BIT(5)
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#define ECMR_DM BIT(1)
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
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/* DMA Descriptors */
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#define RAVB_NUM_BASE_DESC 16
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#define RAVB_NUM_TX_DESC 8
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#define RAVB_NUM_RX_DESC 8
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#define RAVB_TX_QUEUE_OFFSET 0
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#define RAVB_RX_QUEUE_OFFSET 4
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#define RAVB_DESC_DT(n) ((n) << 28)
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#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
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#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
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#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
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#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
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#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
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#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
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#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
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#define RAVB_DESC_DS_MASK 0xfff
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#define RAVB_RX_DESC_MSC_MC BIT(23)
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#define RAVB_RX_DESC_MSC_CEEF BIT(22)
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#define RAVB_RX_DESC_MSC_CRL BIT(21)
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#define RAVB_RX_DESC_MSC_FRE BIT(20)
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#define RAVB_RX_DESC_MSC_RTLF BIT(19)
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#define RAVB_RX_DESC_MSC_RTSF BIT(18)
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#define RAVB_RX_DESC_MSC_RFE BIT(17)
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#define RAVB_RX_DESC_MSC_CRC BIT(16)
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#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
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#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
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(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
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RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
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#define RAVB_TX_TIMEOUT_MS 1000
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struct ravb_desc {
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u32 ctrl;
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u32 dptr;
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};
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struct ravb_rxdesc {
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struct ravb_desc data;
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struct ravb_desc link;
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u8 __pad[48];
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u8 packet[PKTSIZE_ALIGN];
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};
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struct ravb_priv {
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struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
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struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
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struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
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u32 rx_desc_idx;
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u32 tx_desc_idx;
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struct phy_device *phydev;
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struct mii_dev *bus;
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void __iomem *iobase;
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struct clk clk;
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};
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static inline void ravb_flush_dcache(u32 addr, u32 len)
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{
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flush_dcache_range(addr, addr + len);
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}
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static inline void ravb_invalidate_dcache(u32 addr, u32 len)
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{
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u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
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u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(start, end);
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}
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static int ravb_send(struct udevice *dev, void *packet, int len)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
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unsigned int start;
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/* Update TX descriptor */
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ravb_flush_dcache((uintptr_t)packet, len);
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memset(desc, 0x0, sizeof(*desc));
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desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
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desc->dptr = (uintptr_t)packet;
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ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
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/* Restart the transmitter if disabled */
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if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
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setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
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/* Wait until packet is transmitted */
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start = get_timer(0);
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while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
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ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
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if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
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break;
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udelay(10);
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};
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if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
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return -ETIMEDOUT;
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eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
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return 0;
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}
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static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
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int len;
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u8 *packet;
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/* Check if the rx descriptor is ready */
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ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
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if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
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return -EAGAIN;
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/* Check for errors */
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if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
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desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
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return -EAGAIN;
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}
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len = desc->data.ctrl & RAVB_DESC_DS_MASK;
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packet = (u8 *)(uintptr_t)desc->data.dptr;
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ravb_invalidate_dcache((uintptr_t)packet, len);
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*packetp = packet;
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return len;
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}
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static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
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/* Make current descriptor available again */
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desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
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ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
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/* Point to the next descriptor */
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eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
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desc = ð->rx_desc[eth->rx_desc_idx];
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ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
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return 0;
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}
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static int ravb_reset(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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/* Set config mode */
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writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
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/* Check the operating mode is changed to the config mode. */
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return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
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CSR_OPS_CONFIG, true, 100, true);
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}
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static void ravb_base_desc_init(struct ravb_priv *eth)
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{
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const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
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int i;
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/* Initialize all descriptors */
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memset(eth->base_desc, 0x0, desc_size);
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for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
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eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
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ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
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/* Register the descriptor base address table */
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writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
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}
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static void ravb_tx_desc_init(struct ravb_priv *eth)
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{
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const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
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int i;
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/* Initialize all descriptors */
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memset(eth->tx_desc, 0x0, desc_size);
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eth->tx_desc_idx = 0;
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for (i = 0; i < RAVB_NUM_TX_DESC; i++)
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eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
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/* Mark the end of the descriptors */
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eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
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eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
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ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
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/* Point the controller to the TX descriptor list. */
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eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
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eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
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ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
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sizeof(struct ravb_desc));
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}
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static void ravb_rx_desc_init(struct ravb_priv *eth)
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{
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const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
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int i;
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/* Initialize all descriptors */
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memset(eth->rx_desc, 0x0, desc_size);
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eth->rx_desc_idx = 0;
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for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
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eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
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RAVB_DESC_DS(PKTSIZE_ALIGN);
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eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
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eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
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eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
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}
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/* Mark the end of the descriptors */
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eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
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eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
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ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
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/* Point the controller to the rx descriptor list */
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eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
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eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
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ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
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sizeof(struct ravb_desc));
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}
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static int ravb_phy_config(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct phy_device *phydev;
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int mask = 0xffffffff, reg;
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phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
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if (!phydev)
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return -ENODEV;
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phy_connect_dev(phydev, dev);
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eth->phydev = phydev;
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/* 10BASE is not supported for Ethernet AVB MAC */
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phydev->supported &= ~(SUPPORTED_10baseT_Full
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| SUPPORTED_10baseT_Half);
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if (pdata->max_speed != 1000) {
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phydev->supported &= ~(SUPPORTED_1000baseT_Half
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| SUPPORTED_1000baseT_Full);
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reg = phy_read(phydev, -1, MII_CTRL1000);
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reg &= ~(BIT(9) | BIT(8));
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phy_write(phydev, -1, MII_CTRL1000, reg);
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}
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phy_config(phydev);
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return 0;
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}
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/* Set Mac address */
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static int ravb_write_hwaddr(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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unsigned char *mac = pdata->enetaddr;
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writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
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eth->iobase + RAVB_REG_MAHR);
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writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
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return 0;
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}
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/* E-MAC init function */
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static int ravb_mac_init(struct ravb_priv *eth)
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{
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/* Disable MAC Interrupt */
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writel(0, eth->iobase + RAVB_REG_ECSIPR);
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/* Recv frame limit set register */
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writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
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return 0;
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}
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/* AVB-DMAC init function */
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static int ravb_dmac_init(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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int ret = 0;
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/* Set CONFIG mode */
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ret = ravb_reset(dev);
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if (ret)
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return ret;
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/* Disable all interrupts */
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writel(0, eth->iobase + RAVB_REG_RIC0);
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writel(0, eth->iobase + RAVB_REG_RIC1);
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writel(0, eth->iobase + RAVB_REG_RIC2);
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writel(0, eth->iobase + RAVB_REG_TIC);
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/* Set little endian */
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clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
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/* AVB rx set */
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writel(0x18000001, eth->iobase + RAVB_REG_RCR);
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/* FIFO size set */
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writel(0x00222210, eth->iobase + RAVB_REG_TGC);
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/* Delay CLK: 2ns */
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if (pdata->max_speed == 1000)
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writel(BIT(14), eth->iobase + RAVB_REG_APSR);
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return 0;
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}
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static int ravb_config(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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struct phy_device *phy;
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u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
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int ret;
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/* Configure AVB-DMAC register */
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ravb_dmac_init(dev);
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/* Configure E-MAC registers */
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ravb_mac_init(eth);
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ravb_write_hwaddr(dev);
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/* Configure phy */
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ret = ravb_phy_config(dev);
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if (ret)
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return ret;
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phy = eth->phydev;
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ret = phy_startup(phy);
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if (ret)
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return ret;
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/* Set the transfer speed */
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if (phy->speed == 100)
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writel(0, eth->iobase + RAVB_REG_GECMR);
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else if (phy->speed == 1000)
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writel(1, eth->iobase + RAVB_REG_GECMR);
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/* Check if full duplex mode is supported by the phy */
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if (phy->duplex)
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mask |= ECMR_DM;
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writel(mask, eth->iobase + RAVB_REG_ECMR);
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phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
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return 0;
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}
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int ravb_start(struct udevice *dev)
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{
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struct ravb_priv *eth = dev_get_priv(dev);
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int ret;
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ret = clk_enable(ð->clk);
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if (ret)
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return ret;
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ret = ravb_reset(dev);
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if (ret)
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goto err;
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ravb_base_desc_init(eth);
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ravb_tx_desc_init(eth);
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ravb_rx_desc_init(eth);
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ret = ravb_config(dev);
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if (ret)
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goto err;
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/* Setting the control will start the AVB-DMAC process. */
|
|
writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
clk_disable(ð->clk);
|
|
return ret;
|
|
}
|
|
|
|
static void ravb_stop(struct udevice *dev)
|
|
{
|
|
struct ravb_priv *eth = dev_get_priv(dev);
|
|
|
|
ravb_reset(dev);
|
|
clk_disable(ð->clk);
|
|
}
|
|
|
|
static int ravb_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct ravb_priv *eth = dev_get_priv(dev);
|
|
struct mii_dev *mdiodev;
|
|
void __iomem *iobase;
|
|
int ret;
|
|
|
|
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
|
|
eth->iobase = iobase;
|
|
|
|
ret = clk_get_by_index(dev, 0, ð->clk);
|
|
if (ret < 0)
|
|
goto err_mdio_alloc;
|
|
|
|
mdiodev = mdio_alloc();
|
|
if (!mdiodev) {
|
|
ret = -ENOMEM;
|
|
goto err_mdio_alloc;
|
|
}
|
|
|
|
mdiodev->read = bb_miiphy_read;
|
|
mdiodev->write = bb_miiphy_write;
|
|
bb_miiphy_buses[0].priv = eth;
|
|
snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
|
|
|
|
ret = mdio_register(mdiodev);
|
|
if (ret < 0)
|
|
goto err_mdio_register;
|
|
|
|
eth->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
return 0;
|
|
|
|
err_mdio_register:
|
|
mdio_free(mdiodev);
|
|
err_mdio_alloc:
|
|
unmap_physmem(eth->iobase, MAP_NOCACHE);
|
|
return ret;
|
|
}
|
|
|
|
static int ravb_remove(struct udevice *dev)
|
|
{
|
|
struct ravb_priv *eth = dev_get_priv(dev);
|
|
|
|
free(eth->phydev);
|
|
mdio_unregister(eth->bus);
|
|
mdio_free(eth->bus);
|
|
unmap_physmem(eth->iobase, MAP_NOCACHE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_init(struct bb_miiphy_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct ravb_priv *eth = bus->priv;
|
|
|
|
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
|
|
{
|
|
struct ravb_priv *eth = bus->priv;
|
|
|
|
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct ravb_priv *eth = bus->priv;
|
|
|
|
if (v)
|
|
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
|
|
else
|
|
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
|
{
|
|
struct ravb_priv *eth = bus->priv;
|
|
|
|
*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
|
|
{
|
|
struct ravb_priv *eth = bus->priv;
|
|
|
|
if (v)
|
|
setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
|
|
else
|
|
clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ravb_bb_delay(struct bb_miiphy_bus *bus)
|
|
{
|
|
udelay(10);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
|
{
|
|
.name = "ravb",
|
|
.init = ravb_bb_init,
|
|
.mdio_active = ravb_bb_mdio_active,
|
|
.mdio_tristate = ravb_bb_mdio_tristate,
|
|
.set_mdio = ravb_bb_set_mdio,
|
|
.get_mdio = ravb_bb_get_mdio,
|
|
.set_mdc = ravb_bb_set_mdc,
|
|
.delay = ravb_bb_delay,
|
|
},
|
|
};
|
|
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|
|
|
|
static const struct eth_ops ravb_ops = {
|
|
.start = ravb_start,
|
|
.send = ravb_send,
|
|
.recv = ravb_recv,
|
|
.free_pkt = ravb_free_pkt,
|
|
.stop = ravb_stop,
|
|
.write_hwaddr = ravb_write_hwaddr,
|
|
};
|
|
|
|
int ravb_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const char *phy_mode;
|
|
const fdt32_t *cell;
|
|
int ret = 0;
|
|
|
|
pdata->iobase = devfdt_get_addr(dev);
|
|
pdata->phy_interface = -1;
|
|
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
|
|
NULL);
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdata->max_speed = 1000;
|
|
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
|
if (cell)
|
|
pdata->max_speed = fdt32_to_cpu(*cell);
|
|
|
|
sprintf(bb_miiphy_buses[0].name, dev->name);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id ravb_ids[] = {
|
|
{ .compatible = "renesas,etheravb-r8a7795" },
|
|
{ .compatible = "renesas,etheravb-r8a7796" },
|
|
{ .compatible = "renesas,etheravb-rcar-gen3" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_ravb) = {
|
|
.name = "ravb",
|
|
.id = UCLASS_ETH,
|
|
.of_match = ravb_ids,
|
|
.ofdata_to_platdata = ravb_ofdata_to_platdata,
|
|
.probe = ravb_probe,
|
|
.remove = ravb_remove,
|
|
.ops = &ravb_ops,
|
|
.priv_auto_alloc_size = sizeof(struct ravb_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|