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On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
267 lines
7.6 KiB
C
267 lines
7.6 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u8 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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#ifdef CONFIG_PPC_B4860
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x02, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x04, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x05, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x06, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x08, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x09, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x0A, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x0B, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x0C, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2F, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x30, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x32, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x33, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x34, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x39, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x3A, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x3C, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x3D, {AURORA, AURORA, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x5C, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{0x5D, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1} },
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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AURORA, AURORA, SRIO1, SRIO1} },
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{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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AURORA, AURORA, SRIO1, SRIO1} },
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{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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AURORA, AURORA,
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SRIO1, SRIO1}},
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{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1} },
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{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
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SRIO1, SRIO1, SRIO1, SRIO1} },
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{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2, AURORA, AURORA,
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XFI_FM1_MAC9, XFI_FM1_MAC10} },
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{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2, AURORA, AURORA,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2, AURORA, AURORA,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10} },
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{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10} },
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{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0x9A, {PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10} },
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{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{}
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};
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#endif
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#ifdef CONFIG_PPC_B4420
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static struct serdes_config serdes1_cfg_tbl[] = {
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{0x0D, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x0E, {NONE, NONE, CPRI8, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x0F, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x18, {NONE, NONE,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x1B, {NONE, NONE,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x1E, {NONE, NONE, AURORA, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x21, {NONE, NONE, AURORA, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x3E, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, AURORA, NONE, NONE, NONE, NONE} },
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{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, AURORA, NONE, NONE, NONE, NONE} },
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{0x9A, {PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
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NONE, NONE, NONE, NONE} },
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{}
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};
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#endif
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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serdes2_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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