mirror of
https://github.com/AsahiLinux/u-boot
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656d8da9d2
Commit ad7061ed74 ("doc: Move device tree bindings documentation to
doc/device-tree-bindings") moved all device tree binding documentation
to doc/device-tree-bindings directory.
The current U-Boot project still have two documentation directories:
- doc/
- Documentation/
Move all documentation and sphinx files to doc directory so all content
can be in a common place.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
314 lines
14 KiB
Text
314 lines
14 KiB
Text
MPC83xx RAM controller
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This driver supplies support for the embedded RAM controller on MCP83xx-series
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SoCs.
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For static configuration mode, each controller node should have child nodes
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describing the actual RAM modules installed.
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Controller node
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===============
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Required properties:
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- compatible: Must be "fsl,mpc83xx-mem-controller"
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- reg: The address of the RAM controller's register space
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- #address-cells: Must be 2
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- #size-cells: Must be 1
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- driver_software_override: DDR driver software override is enabled (1) or
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disabled (0)
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- p_impedance_override: DDR driver software p-impedance override; possible
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values:
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* DSO_P_IMPEDANCE_HIGHEST_Z
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* DSO_P_IMPEDANCE_MUCH_HIGHER_Z
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* DSO_P_IMPEDANCE_HIGHER_Z
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* DSO_P_IMPEDANCE_NOMINAL
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* DSO_P_IMPEDANCE_LOWER_Z
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- n_impedance_override: DDR driver software n-impedance override; possible
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values:
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* DSO_N_IMPEDANCE_HIGHEST_Z
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* DSO_N_IMPEDANCE_MUCH_HIGHER_Z
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* DSO_N_IMPEDANCE_HIGHER_Z
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* DSO_N_IMPEDANCE_NOMINAL
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* DSO_N_IMPEDANCE_LOWER_Z
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- odt_termination_value: ODT termination value for I/Os; possible values:
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* ODT_TERMINATION_75_OHM
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* ODT_TERMINATION_150_OHM
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- ddr_type: Selects voltage level for DDR pads; possible
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values:
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* DDR_TYPE_DDR2_1_8_VOLT
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* DDR_TYPE_DDR1_2_5_VOLT
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- mvref_sel: Determine where MVREF_SEL signal is generated;
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possible values:
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* MVREF_SEL_EXTERNAL
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* MVREF_SEL_INTERNAL_GVDD
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- m_odr: Disable memory transaction reordering; possible
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values:
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* M_ODR_ENABLE
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* M_ODR_DISABLE
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- clock_adjust: Clock adjust; possible values:
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* CLOCK_ADJUST_025
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* CLOCK_ADJUST_05
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* CLOCK_ADJUST_075
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* CLOCK_ADJUST_1
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- ext_refresh_rec: Extended refresh recovery time; possible values:
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0, 16, 32, 48, 64, 80, 96, 112
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- read_to_write: Read-to-write turnaround; possible values:
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0, 1, 2, 3
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- write_to_read: Write-to-read turnaround; possible values:
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0, 1, 2, 3
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- read_to_read: Read-to-read turnaround; possible values:
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0, 1, 2, 3
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- write_to_write: Write-to-write turnaround; possible values:
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0, 1, 2, 3
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- active_powerdown_exit: Active powerdown exit timing; possible values:
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1, 2, 3, 4, 5, 6, 7
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- precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
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1, 2, 3, 4, 5, 6, 7
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- odt_powerdown_exit: ODT powerdown exit timing; possible values:
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0, 1, 2, 3, 4, 5, 6, 7, 8,
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9, 10, 11, 12, 13, 14, 15
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- mode_reg_set_cycle: Mode register set cycle time; possible values:
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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- precharge_to_activate: Precharge-to-acitvate interval; possible values:
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1, 2, 3, 4, 5, 6, 7
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- activate_to_precharge: Activate to precharge interval; possible values:
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4, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 18, 19
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- activate_to_readwrite: Activate to read/write interval for SDRAM;
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possible values:
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1, 2, 3, 4, 5, 6, 7
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- mcas_latency: MCAS latency from READ command; possible values:
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* CASLAT_20
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* CASLAT_25
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* CASLAT_30
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* CASLAT_35
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* CASLAT_40
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* CASLAT_45
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* CASLAT_50
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* CASLAT_55
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* CASLAT_60
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* CASLAT_65
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* CASLAT_70
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* CASLAT_75
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* CASLAT_80
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- refresh_recovery: Refresh recovery time; possible values:
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23
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- last_data_to_precharge: Last data to precharge minimum interval; possible
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values:
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1, 2, 3, 4, 5, 6, 7
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- activate_to_activate: Activate-to-activate interval; possible values:
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1, 2, 3, 4, 5, 6, 7
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- last_write_data_to_read: Last write data pair to read command issue
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interval; possible values:
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1, 2, 3, 4, 5, 6, 7
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- additive_latency: Additive latency; possible values:
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0, 1, 2, 3, 4, 5
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- mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
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* READ_LAT
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* READ_LAT_PLUS_1_4
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* READ_LAT_PLUS_1_2
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* READ_LAT_PLUS_3_4
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* READ_LAT_PLUS_1
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* READ_LAT_PLUS_5_4
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* READ_LAT_PLUS_3_2
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* READ_LAT_PLUS_7_4
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* READ_LAT_PLUS_2
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* READ_LAT_PLUS_9_4
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* READ_LAT_PLUS_5_2
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* READ_LAT_PLUS_11_4
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* READ_LAT_PLUS_3
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* READ_LAT_PLUS_13_4
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* READ_LAT_PLUS_7_2
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* READ_LAT_PLUS_15_4
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* READ_LAT_PLUS_4
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* READ_LAT_PLUS_17_4
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* READ_LAT_PLUS_9_2
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* READ_LAT_PLUS_19_4
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- write_latency: Write latency; possible values:
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1, 2, 3, 4, 5, 6, 7
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- read_to_precharge: Read to precharge; possible values:
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1, 2, 3, 4
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- write_cmd_to_write_data: Write command to write data strobe timing
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adjustment; possible values:
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* CLOCK_DELAY_0
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* CLOCK_DELAY_1_4
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* CLOCK_DELAY_1_2
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* CLOCK_DELAY_3_4
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* CLOCK_DELAY_1
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* CLOCK_DELAY_5_4
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* CLOCK_DELAY_3_2
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- minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
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1, 2, 3, 4
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- four_activates_window: Window for four activates; possible values:
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1, 2, 3, 4 8, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 18, 19
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- self_refresh: Self refresh (during sleep); possible values:
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* SREN_DISABLE
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* SREN_ENABLE
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- ecc: Support for ECC; possible values:
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* ECC_DISABLE
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* ECC_ENABLE
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- registered_dram: Support for registered DRAM; possible values:
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* RD_DISABLE
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* RD_ENABLE
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- sdram_type: Type of SDRAM device to be used; possible values:
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* TYPE_DDR1
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* TYPE_DDR2
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- dynamic_power_management: Dynamic power management mode; possible values:
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* DYN_PWR_DISABLE
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* DYN_PWR_ENABLE
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- databus_width: DRAM data bus width; possible values
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* DATA_BUS_WIDTH_16
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* DATA_BUS_WIDTH_32
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- nc_auto_precharge: Non-concurrent auto-precharge; possible values:
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* NCAP_DISABLE
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* NCAP_ENABLE
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- timing_2t: 2T timing; possible values:
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* TIMING_1T
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* TIMING_2T
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- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
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values:
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* INTERLEAVE_NONE
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* INTERLEAVE_1_AND_2
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- precharge_bit_8: Precharge bin 8; possible values
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* PRECHARGE_MA_10
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* PRECHARGE_MA_8
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- half_strength: Global half-strength override; possible values:
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* STRENGTH_FULL
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* STRENGTH_HALF
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- bypass_initialization: Bypass initialization; possible values:
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* INITIALIZATION_DONT_BYPASS
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* INITIALIZATION_BYPASS
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- force_self_refresh: Force self refresh; possible values:
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* MODE_NORMAL
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* MODE_REFRESH
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- dll_reset: DLL reset; possible values:
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* DLL_RESET_ENABLE
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* DLL_RESET_DISABLE
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- dqs_config: DQS configuration; possible values:
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* DQS_TRUE
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- odt_config: ODT configuration; possible values:
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* ODT_ASSERT_NEVER
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* ODT_ASSERT_WRITES
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* ODT_ASSERT_READS
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* ODT_ASSERT_ALWAYS
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- posted_refreshes: Number of posted refreshes
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1, 2, 3, 4, 5, 6, 7, 8
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- sdmode: Initial value loaded into the DDR SDRAM mode
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register
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- esdmode: Initial value loaded into the DDR SDRAM extended
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mode register
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- esdmode2: Initial value loaded into the DDR SDRAM extended
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mode 2 register
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- esdmode3: Initial value loaded into the DDR SDRAM extended
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mode 3 register
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- refresh_interval: Refresh interval; possible values:
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0 - 65535
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- precharge_interval: Precharge interval; possible values:
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0 - 16383
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RAM module node:
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================
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Required properties:
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- reg: A triple <cs addr size>, which consists of:
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* cs - the chipselect used to drive this RAM module
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* addr - the address where this RAM module's memory is map
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to in the global memory space
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* size - the size of the RAM module's memory in bytes
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- auto_precharge: Chip select auto-precharge; possible values:
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* AUTO_PRECHARGE_ENABLE
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* AUTO_PRECHARGE_DISABLE
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- odt_rd_cfg: ODT for reads configuration; possible values:
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* ODT_RD_NEVER
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* ODT_RD_ONLY_CURRENT
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* ODT_RD_ONLY_OTHER_CS
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* ODT_RD_ONLY_OTHER_DIMM
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* ODT_RD_ALL
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- odt_wr_cfg: ODT for writes configuration; possible values:
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* ODT_WR_NEVER
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* ODT_WR_ONLY_CURRENT
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* ODT_WR_ONLY_OTHER_CS
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* ODT_WR_ONLY_OTHER_DIMM
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* ODT_WR_ALL
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- bank_bits: Number of bank bits for SDRAM on chip select; possible
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values:
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2, 3
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- row_bits: Number of row bits for SDRAM on chip select; possible values:
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12, 13, 14
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- col_bits: Number of column bits for SDRAM on chip select; possible
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values:
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8, 9, 10, 11
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Example:
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memory@2000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc83xx-mem-controller";
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reg = <0x2000 0x1000>;
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device_type = "memory";
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u-boot,dm-pre-reloc;
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driver_software_override = <DSO_ENABLE>;
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p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
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n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
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odt_termination_value = <ODT_TERMINATION_150_OHM>;
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ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
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clock_adjust = <CLOCK_ADJUST_05>;
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read_to_write = <0>;
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write_to_read = <0>;
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read_to_read = <0>;
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write_to_write = <0>;
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active_powerdown_exit = <2>;
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precharge_powerdown_exit = <6>;
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odt_powerdown_exit = <8>;
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mode_reg_set_cycle = <2>;
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precharge_to_activate = <2>;
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activate_to_precharge = <6>;
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activate_to_readwrite = <2>;
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mcas_latency = <CASLAT_40>;
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refresh_recovery = <17>;
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last_data_to_precharge = <2>;
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activate_to_activate = <2>;
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last_write_data_to_read = <2>;
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additive_latency = <0>;
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mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
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write_latency = <3>;
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read_to_precharge = <2>;
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write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
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minimum_cke_pulse_width = <3>;
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four_activates_window = <5>;
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self_refresh = <SREN_ENABLE>;
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sdram_type = <TYPE_DDR2>;
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databus_width = <DATA_BUS_WIDTH_32>;
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force_self_refresh = <MODE_NORMAL>;
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dll_reset = <DLL_RESET_ENABLE>;
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dqs_config = <DQS_TRUE>;
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odt_config = <ODT_ASSERT_READS>;
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posted_refreshes = <1>;
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refresh_interval = <2084>;
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precharge_interval = <256>;
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sdmode = <0x0242>;
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esdmode = <0x0440>;
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ram@0 {
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reg = <0x0 0x0 0x8000000>;
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compatible = "nanya,nt5tu64m16hg";
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odt_rd_cfg = <ODT_RD_NEVER>;
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odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
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bank_bits = <3>;
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row_bits = <13>;
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col_bits = <10>;
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};
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};
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