mirror of
https://github.com/AsahiLinux/u-boot
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e6f48aad15
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by Kontron Electronics GmbH. Currently there are the following SoM flavors (SoM-Line): * N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND * N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND * N6411: SOM with i.MX6ULL, 512MB RAM, 512MB SPI NAND And the according evaluation boards (Board-Line): * N6310-S: Baseboard with SOM N6310, eMMC, display (optional), ... * N6311-S: Baseboard with SOM N6311, eMMC, display (optional), ... * N6411-S: Baseboard with SOM N6411, eMMC, display (optional), ... Currently U-Boot describes i.MX6UL and i.MX6ULL through separate config options at compile-time. Though the differences are so minor, that for the scope of these SoMs we just use a single defconfig that is compatible with both SoCs. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
85 lines
1.5 KiB
C
85 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Kontron Electronics GmbH
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <fdt_support.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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/*
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* Overwrite the memory size in the devicetree that is
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* passed to the kernel with the actual size detected.
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*/
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return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
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}
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static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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/*
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* Use 50M anatop loopback REF_CLK1 for ENET1,
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* clear gpr1[13], set gpr1[17].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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/*
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* Use 50M anatop loopback REF_CLK2 for ENET2,
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* clear gpr1[14], set gpr1[18].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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return ret;
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_early_init_f(void)
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{
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enable_qspi_clk(0);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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setup_fec();
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return 0;
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}
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