mirror of
https://github.com/AsahiLinux/u-boot
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5e5cfaf997
Add the USB ehci support for the OMAP5 uEVM. Configure the uEVM mux data Add the flags to build the appropriate modules Add the usb call backs to initialize the EHCI controller Signed-off-by: Dan Murphy <dmurphy@ti.com>
292 lines
14 KiB
C
292 lines
14 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _EVM5430_MUX_DATA_H
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#define _EVM5430_MUX_DATA_H
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#include <asm/arch/mux_omap5.h>
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const struct pad_conf_entry core_padconf_array_essential[] = {
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{EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
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{EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
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{EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
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{EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
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{EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
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{EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
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{EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
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{EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
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{EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
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{EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
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{SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
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{SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
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{SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
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{SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
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{SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
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{SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
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{UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
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{UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
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{USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
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{USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
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{USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
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{USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
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{USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
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{USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
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{USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
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{USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
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{USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
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{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
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{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
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{HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
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{HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
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};
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const struct pad_conf_entry wkup_padconf_array_essential[] = {
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{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
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{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
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{SYS_32K, (IEN | M0)}, /* SYS_32K */
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{FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
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};
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const struct pad_conf_entry core_padconf_array_non_essential[] = {
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{C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */
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{C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */
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{C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */
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{C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */
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{C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */
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{C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */
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{C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */
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{C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */
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{C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */
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{C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */
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{C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */
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{C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */
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{C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */
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{C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */
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{C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */
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{C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */
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{C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */
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{C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */
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{C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */
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{C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */
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{C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */
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{C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */
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{C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */
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{C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */
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{C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */
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{C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */
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{C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */
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{C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */
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{LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */
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{LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */
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{HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */
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{HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */
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{HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */
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{HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */
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{HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */
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{HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */
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{HSI1_CAFLAG, (M6)}, /* GPIO3_70 */
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{HSI1_CADATA, (M6)}, /* GPIO3_71 */
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{UART1_TX, (M0)}, /* UART1_TX */
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{UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */
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{UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */
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{UART1_RTS, (M0)}, /* UART1_RTS */
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{HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */
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{HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */
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{HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */
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{HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */
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{HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */
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{HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */
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{HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */
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{HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */
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{UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */
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{UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */
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{UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */
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{UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */
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{TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */
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{DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */
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{DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */
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{DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */
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{DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */
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{DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */
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{DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */
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{DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */
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{DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */
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{DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */
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{DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */
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{DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */
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{TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */
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{DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */
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{DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */
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{DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */
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{DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */
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{DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */
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{DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */
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{DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */
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{DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */
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{DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */
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{DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */
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{DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */
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{RFBI_HSYNC0, (M4)}, /* KBD_COL5 */
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{RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */
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{RFBI_RE, (M4)}, /* KBD_COL4 */
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{RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */
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{RFBI_DATA8, (M4)}, /* KBD_COL3 */
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{RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */
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{RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */
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{RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */
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{RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */
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{RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */
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{RFBI_DATA14, (M4)}, /* KBD_COL7 */
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{RFBI_DATA15, (M4)}, /* KBD_COL6 */
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{GPIO6_182, (M6)}, /* GPIO6_182 */
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{GPIO6_183, (PTD | M6)}, /* GPIO6_183 */
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{GPIO6_184, (M4)}, /* KBD_COL2 */
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{GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */
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{GPIO6_186, (PTD | M6)}, /* GPIO6_186 */
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{GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */
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{RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */
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{RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */
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{RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */
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{RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */
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{RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */
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{RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */
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{RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */
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{RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */
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{RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */
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{RFBI_WE, (PTD | M6)}, /* GPIO6_162 */
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{MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */
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{MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */
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{MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/
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{MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/
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{I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */
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{I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */
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{HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */
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{HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */
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{HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */
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{HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */
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{CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */
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{CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */
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{CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */
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{CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */
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{CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */
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{CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */
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{CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */
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{CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */
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{CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */
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{CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */
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{CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */
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{CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */
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{CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */
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{CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */
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{CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */
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{CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */
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{CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */
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{CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */
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{CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */
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{CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */
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{CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */
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{CAM_STROBE, (M0)}, /* CAM_STROBE */
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{CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */
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{TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */
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{TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */
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{TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */
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{TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */
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{I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */
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{I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */
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{GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */
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{ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */
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{ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */
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{ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */
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{ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */
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{ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */
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{ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */
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{ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */
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{ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */
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{ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */
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{ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */
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{ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */
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{ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */
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{ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */
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{ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */
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{ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */
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{ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */
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{ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */
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{WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */
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{WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */
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{WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/
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{WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/
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{WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/
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{WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/
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{UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */
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{UART5_TX, (M0)}, /* UART5_TX */
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{UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */
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{UART5_RTS, (M0)}, /* UART5_RTS */
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{I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */
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{I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */
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{MCSPI1_CLK, (M6)}, /* GPIO5_140 */
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{MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */
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{MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */
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{MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */
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{MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */
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{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
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{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
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{PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */
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{PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */
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{UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */
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{UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */
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{UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */
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{UART6_RTS, (PTU | M0)}, /* UART6_RTS */
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{UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */
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{UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */
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{I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
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{I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
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};
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const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
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/*
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* This pad keeps C2C Module always enabled.
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* Putting this in safe mode do not cause the issue.
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* C2C driver could enable this mux setting if needed.
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*/
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{LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */
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{LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */
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{DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */
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{DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */
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{JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */
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{JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */
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{JTAG_RTCK, (M0)}, /* JTAG_RTCK */
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{JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */
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{JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */
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{JTAG_TDO, (M0)}, /* JTAG_TDO */
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{FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */
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{FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */
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{FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */
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{FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */
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{FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */
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{FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */
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{SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */
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{SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */
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{SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */
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{SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */
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{SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */
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{SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */
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{SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */
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{SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */
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{SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */
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{SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */
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{SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */
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};
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#endif /* _EVM4430_MUX_DATA_H */
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